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Unformatted text preview: memory attributes of the paging hierarchy. Note that all 8 PAT entries are available for describing a 4 KB/2 MB/4 MB page. The memory type as now defined by PAT interacts with the MTRR memory type to determine the effective memory type as outlined in Table 9-9. Compare this to Table 9-5. 9-36 MEMORY CACHE CONTROL Table 9-9. Effective Memory Type Depending on MTRRs and PAT
PAT Memory Type UCMTRR Memory Type WB, WT WC UC WP UC WC WT WB, WT, WP, WC UC X WB, WT UC WC WP WP WB, WP UC WC, WT WB WB UC WC WT WP NOTES: • This table assumes that the CD and NW flags in register CR0 are set to 0. If CR0.CD = 1, then the effective memory type returned is UC, regardless of what is indicated in the table. However, this does not force strict ordering. To ensure strict ordering, the MTRRs also must be disabled. • The effective memory types in the gray areas are implementation dependent and may be different between implementations of Intel Architecture processors. • UC_MTRR indicates that the UC attribute came from the MTRRs and the processor(s) are not required to snoop their caches since the data could never have been cached. This is preferred for performance reasons. • UC_PAGE indicates that the UC attribute came from the page tables and processors are required to check their caches because the data may be cached due to page aliasing, which is not recommended. • UC- is the page encoding PCD, PWT = 10 on P6 family processors that do not support this feature. UC- in the PTE/PDE is overridden by WC in the MTRRs. • UC is the page encoding PCD, PWT = 11 on P6 family processors that do not support this feature. UC in the PTE/PDE overrides WC in the MTRRs. Effective Memory Type UC_PAGE WC UC_MTRR Undefined UC_PAGE UC_MTRR WC WT UC_MTRR Undefined Undefined WP UC_MTRR Undefined WB UC_MTRR WC WT WP Whenever the MTRRs are disabled, via bit 11 (E) in the MTRRDefType register, the effective memory type is UC for all memory ranges. An operating system can program the PAT and select the 8 most useful attribute combinations. The PAT allows an operating system to offer performance-enhancing memory types to applications. 9-37 MEMORY CACHE CONTROL The page attribute for addresses containing a page directory or page table supports only the first four entries in the PAT, since a PAT-index bit is not defined for these mappings. The page attribute is determined by using the two-bit value specified by PCD and PWT in CR3 (for page directory) or the page-directory entry (for page tables). The same applies to Page-DirectoryPointer Tables when PAE is enabled. 9.13.5. Programming the PAT
The Page Attribute Table is read/write accessible to software operating at ring 0 through the use of the rdmsr and wrmsr instructions. Accesses are directed to the PAT through use of model specific register address 277H. Refer to Figure 9-7 for the format of the 64-bit register containing the PAT. The PAT implementation on processors that support the feature defines only the 3 least significant bits for page attributes. These bits are used to specify the memory type with the same encoding as used for the P6 family MTRRs as shown in Table 9-6. Processors that support the PAT feature modify those encodings slightly, in that encoding 0 is UC and encoding 7 is UC-, as indicated in the Table 9-10. Encoding 7 remains undefined for the fixed and variable MTRRs, and any attempt to write an undefined memory type encoding continues to generate a GP fault. Attempting to write an undefined memory type encoding into the PAT generates a GP fault.
Table 9-10. PAT Memory Types and Their Properties
Writeback Cacheable No No No Allows Speculative Reads No Yes Yes Memory Ordering Model Strong Ordering Weak Ordering Speculative Processor Ordering Speculative Processor Ordering Speculative Processor Ordering Strong Ordered, but can be overridden by WC in the MTRRs Mnemonic Uncacheable (UC) Write Combining (WC) Write-through (WT) Write-protect (WP) Write-back (WB) Encoding 0 1 4 Cacheable No No Yes 5 Yes for reads, no for writes Yes No Yes 6 Yes Yes Uncached (UC-) 7 No No No Reserved 2, 3, 87-255 The operating system is responsible for ensuring that changes to a PAT entry occur in a manner that maintains the consistency of the processor caches and translation lookaside buffers (TLB). This is accomplished by following the procedure as specified in the Intel Architecture Software 9-38 MEMORY CACHE CONTROL Developer’s Manual, Volume 3: System Programming Guide, for changing the value of an MTRR. It involves a specific sequence of operations that includes flushing the processor(s) caches and TLBs. An operating system must ensure that the PAT of all processors in a multiprocessing system have the same values. The PAT allows any memory type to be specified in the page tables, and therefore it is possible to have a single physical page mapped by two different linear addresses with differing memory types. This practice is strongly discouraged by Intel and should be avoided as it may lead to undefined results. In particular, a WC page must never be aliased to a cacheable page because WC writes may not check the processor caches. W...
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