See table 9 6 for the encoding of this field

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: the memory type for each of the subranges the register controls. Table 9-7 shows the relationship between the fixed physical-address ranges and the corresponding fields of the fixed-range MTRRs; Table 9-6 shows the encoding of these field: • Register MTRRfix64K_00000. Maps the 512-KByte address range from 0H to 7FFFFH. This range is divided into eight 64-KByte sub-ranges. 9-22 MEMORY CACHE CONTROL • • Registers MTRRfix16K_80000 and MTRRfix16K_A0000. Maps the two 128-KByte address ranges from 80000H to BFFFFH. This range is divided into sixteen 16-KByte subranges, 8 ranges per register. Registers MTRRfix4K_C0000. and MTRRfix4K_F8000. Maps eight 32-KByte address ranges from C0000H to FFFFFH. This range is divided into sixty-four 4-KByte subranges, 8 ranges per register. See the Pentium® Pro BIOS Writer’s Guide for examples of assigning memory types with fixedrange MTRRs. Table 9-7. Address Mapping for Fixed-Range MTRRs Address Range (hexadecimal) 63 56 700007FFFF 9C000 9FFFF BC000 BFFFF C7000 C7FFF CF000 CFFFF D7000 D7FFF DF000 DFFFF E7000 E7FFF EF000 EFFFF F7000 F7FFF FF000 FFFFF 55 48 47 40 39 32 31 24 23 16 15 8 7 0 MTRRfix64K _00000 MTRRfix16K _80000 MTRRfix16K _A0000 MTRRfix4K_ C0000 MTRRfix4K_ C8000 MTRRfix4K_ D0000 MTRRfix4K_ D8000 MTRRfix4K_ E0000 MTRRfix4K_ E8000 MTRRfix4K_ F0000 MTRRfix4K_ F8000 Register 600006FFFF 9800098FFF B8000BBFFF C6000C6FFF CE000CEFFF D6000D6FFF DE000DEFFF E6000E6FFF EE000EEFFF F6000F6FFF FE000FEFFF 500005FFFF 9400097FFF B4000B7FFF C5000C5FFF CD000CDFFF D5000D5FFF DD000DDFFF E5000E5FFF ED000EDFFF F5000F5FFF FD000FDFFF 400004FFFF 9000093FFF B0000B3FFF C4000C4FFF CC000CCFFF D4000D4FFF DC000DCFFF E4000E4FFF EC000ECFFF F4000F4FFF FC000FCFFF 300003FFFF 8C0008FFFF AC000AFFFF C3000C3FFF CB000CBFFF D3000D3FFF DB000DBFFF E3000E3FFF EB000EBFFF F3000F3FFF FB000FBFFF 200002FFFF 880008BFFF A8000ABFFF C2000C2FFF CA000CAFFF D2000D2FFF DA000DAFFF E2000E2FFF EA000EAFFF F2000F2FFF FA000FAFFF 100001FFFF 8400087FFF A4000A7FFF C1000C1FFF C9000C9FFF D1000D1FFF D9000D9FFF E1000E1FFF E9000E9FFF F1000F1FFF F9000F9FFF 000000FFFF 8000083FFF A0000A3FFF C0000C0FFF C8000C8FFF D0000D0FFF D8000D8FFF E0000E0FFF E8000E8FFF F0000F0FFF F8000F8FFF VARIABLE RANGE MTRRS The P6 family processors permit software to specify the memory type for eight variable-size address ranges, using a pair of MTRRs for each range. The first of each pair (MTRRphysBasen) defines the base address and memory type for the range, and the second (MTRRphysMaskn) contains a mask that is used to determine the address range. The “n” suffix indicates registers pairs 0 through 7. Figure 9-6 shows flags and fields in these registers. The functions of the flags and fields in these registers are as follows: 9-23 MEMORY CACHE CONTROL Type field, bits 0 through 7 Specifies the memory type for the range. See Table 9-6 for the encoding of this field. MTRRphysBasen Register 63 36 35 12 11 87 0 Reserved PhysBase Type PhysBase—Base address of range Type—Memory type for range MTRRphysMaskn Register 63 36 35 12 11 10 0 Reserved PhysMask V Reserved PhysMask—Sets range mask V—Valid Reserved Figure 9-6. MTRRphysBasen and MTRRphysMaskn Variable-Range Register Pair PhysBase field, bits 12 through 35 Specifies the base address of the address range. This 24-bit value is extended by 12 bits at the low end to form the base address, which automatically aligns the address on a 4-KByte boundary. PhysMask field, bits 12 through 35 Specifies a 24-bit mask that determines the range of the region being mapped, according to the following relationship: Address_Within_Range AND PhysMask = PhysBase AND PhysMask This 24-bit value is extended by 12 bits at the low end to form the mask value. See Section 9.12.3., “Example Base and Mask Calculations”, for more information and some examples of base address and mask computations. V (valid) flag, bit 11 Enables the register pair when set; disables register pair when clear. All other bits in the MTRRphysBasen and MTRRphysMaskn registers are reserved; the processor generates a general-protection exception (#GP) if software attempts to write to them. Overlapping variable MTRR ranges are not supported generically. However, two variable ranges are allowed to overlap, if the following conditions are present: • If both of them are UC (uncached). 9-24 MEMORY CACHE CONTROL • If one range is of type UC and the other is of type WB (write back). In both cases above, the effective type for the overlapping region is UC. The processor’s behavior is undefined for all other cases of overlapping variable ranges. A variable range can overlap a fixed range (provided the fixed range MTRR’s are enabled). Here, the memory type specified in the fixed range register overrides the one specified in variable-range register pair. NOTE Some mask values can result in discontinuous ranges. In a discontinuous range, the area not mapped by the mask value is set to the default memory type. Intel does not encourage the use of discontinuous ranges, because they co...
View Full Document

Ask a homework question - tutors are online