IntelSoftwareDevelopersManual

Selectors4 pwr up or reset 00 finitfninit unchanged

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Unformatted text preview: nonzero value in the EAX register after the BIST indicates that a processor fault was detected. If the BIST is not requested, the contents of the EAX register after a hardware reset is 0H. The overhead for performing a BIST varies between processor families. For example, the BIST takes approximately 5.5 million processor clock periods to execute on the Pentium® Pro processor. (This clock count is model-specific, and Intel reserves the right to change the exact number of periods, for any of the Intel Architecture processors, without notification.) 8-2 PROCESSOR MANAGEMENT AND INITIALIZATION Table 8-1. 32-Bit Intel Architecture Processor States Following Power-up, Reset, or INIT Register EFLAGS1 EIP CR0 CR2, CR3, CR4 MXCSR P6 Family Processors 00000002H 0000FFF0H 60000010H 00000000H Pentium III processor onlyPwr up or Reset: 1F80H FINIT/FNINIT: Unchanged Selector = F000H Base = FFFF0000H Limit = FFFFH AR = Present, R/W, Accessed Selector = 0000H Base = 00000000H Limit = FFFFH AR = Present, R/W, Accessed 000006xxH 0 3 Pentium® Processor 00000002H 0000FFF0H 60000010H 00000000H NA 2 Intel486™ Processor 00000002H 0000FFF0H 60000010H2 00000000H NA 2 ® CS Selector = F000H Base = FFFF0000H Limit = FFFFH AR = Present, R/W, Accessed Selector = 0000H Base = 00000000H Limit = FFFFH AR = Present, R/W, Accessed 000005xxH 0 3 Selector = F000H Base = FFFF0000H Limit = FFFFH AR = Present, R/W, Accessed Selector = 0000H Base = 00000000H Limit = FFFFH AR = Present, R/W, Accessed 000004xxH 03 00000000H NA SS, DS, ES, FS, GS EDX EAX EBX, ECX, ESI, EDI, EBP, ESP MM0 through MM74 00000000H Pentium® Pro processor NA Pentium® II and Pentium® III processor Pwr up or Reset: 0000000000000000H FINIT/FNINIT: Unchanged Pentium® III processor onlyPwr up or Reset: 0000000000000000H FINIT/FNINIT: Unchanged Pwr up or Reset: +0.0 FINIT/FNINIT: Unchanged Pwr up or Reset: 0040H FINIT/FNINIT: 037FH Pwr up or Reset: 0000H FINIT/FNINIT: 0000H Pwr up or Reset: 5555H FINIT/FNINIT: FFFFH Pwr up or Reset: 0000H FINIT/FNINIT: 0000H 00000000H Pwr up or Reset: 0000000000000000H FINIT/FNINIT: Unchanged XMM0 through XMM75 NA NA ST0 through ST74 FPU Control Word4 FPU Status Word4 FPU Tag Word4 FPU Data Operand and CS Seg. Selectors4 Pwr up or Reset: +0.0 FINIT/FNINIT: Unchanged Pwr up or Reset: 0040H FINIT/FNINIT: 037FH Pwr up or Reset: 0000H FINIT/FNINIT: 0000H Pwr up or Reset: 5555H FINIT/FNINIT: FFFFH Pwr up or Reset: 0000H FINIT/FNINIT: 0000H Pwr up or Reset: +0.0 FINIT/FNINIT: Unchanged Pwr up or Reset: 0040H FINIT/FNINIT: 037FH Pwr up or Reset: 0000H FINIT/FNINIT: 0000H Pwr up or Reset: 5555H FINIT/FNINIT: FFFFH Pwr up or Reset: 0000H FINIT/FNINIT: 0000H 8-3 PROCESSOR MANAGEMENT AND INITIALIZATION Table 8-1. 32-Bit Intel Architecture Processor States Following Power-up, Reset, or INIT (Contd.) Register FPU Data Operand and Inst. Pointers4 GDTR,IDTR P6 Family Processors Pwr up or Reset: 00000000H FINIT/FNINIT: 00000000H Base = 00000000H Limit = FFFFH AR = Present, R/W Selector = 0000H Base = 00000000H Limit = FFFFH AR = Present, R/W 00000000H FFFF0FF0H 00000400H Power up or Reset: 0H INIT: Unchanged Power up or Reset: 0H INIT: Unchanged Pwr up or Reset: Undefined INIT: Unchanged Invalid Pwr up or Reset: Disabled INIT: Unchanged Pwr up or Reset: Disabled INIT: Unchanged Pwr up or Reset: Undefined INIT: Unchanged Pwr up or Reset: Enabled INIT: Unchanged Pentium® Processor Pwr up or Reset: 00000000H FINIT/FNINIT: 00000000H Base = 00000000H Limit = FFFFH AR = Present, R/W Selector = 0000H Base = 00000000H Limit = FFFFH AR = Present, R/W 00000000H FFFF0FF0H 00000400H Power up or Reset: 0H INIT: Unchanged Power up or Reset: 0H INIT: Unchanged Pwr up or Reset: Undefined INIT: Unchanged Invalid Not Implemented Not Implemented Not Implemented Intel486™ Processor Pwr up or Reset: 00000000H FINIT/FNINIT: 00000000H Base = 00000000H Limit = FFFFH AR = Present, R/W Selector = 0000H Base = 00000000H Limit = FFFFH AR = Present, R/W 00000000H FFFF1FF0H 00000000H Not Implemented Not Implemented LDTR, Task Register DR0, DR1, DR2, DR3 DR6 DR7 Time-Stamp Counter Perf. Counters and Event Select All Other MSRs Not Implemented Data and Code Cache, TLBs Fixed MTRRs Variable MTRRs Machine-Check Architecture APIC Invalid Not Implemented Not Implemented Not Implemented Pwr up or Reset: Enabled INIT: Unchanged Not Implemented NOTES: 1. The 10 most-significant bits of the EFLAGS register are undefined following a reset. Software should not depend on the states of any of these bits. 2. The CD and NW flags are unchanged, bit 4 is set to 1, all other bits are cleared. 3. If Built-In Self-Test (BIST) is invoked on power up or reset, EAX is 0 only if all tests passed. (BIST cannot be invoked during an INIT.) 4. The state of the FPU state and MMX™ registers is not changed by the execution of an INIT. 5. Available in the Pentium® III processor and Pentium® III Xeon™ processor only. The state of the SIMD floating-point registers is not changed by the execution of an INIT. 8-4 PROCESSOR MANAGEMENT AND INITIALIZA...
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