IntelSoftwareDevelopersManual

Set by software to indicate that an interrupt is

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: flag. This flag is used in conjunction with the VIP flag. The processor only recognizes the VIF flag when either the VME flag or the PVI flag in control register CR4 is set and the IOPL is less than 3. (The VME flag enables the virtual-8086 mode extensions; the PVI flag enables the protected-mode virtual interrupts.) Refer to Section 16.3.3.5., “Method 6: Software Interrupt Handling” and Section 16.4., “Protected-Mode Virtual Interrupts” in Chapter 16, 8086 Emulation for detailed information about the use of this flag. Virtual interrupt pending (bit 20). Set by software to indicate that an interrupt is pending; cleared to indicate that no interrupt is pending. This flag is used in conjunction with the VIF flag. The processor reads this flag but never modifies it. The processor only recognizes the VIP flag when either the VME flag or the PVI flag in control register CR4 is set and the IOPL is less than 3. (The VME flag enables the virtual-8086 mode extensions; the PVI flag enables the protected-mode virtual interrupts.) Refer to Section 16.3.3.5., “Method 6: Software Interrupt Handling” and Section 16.4., “Protected-Mode Virtual Interrupts” in Chapter 16, 8086 Emulation for detailed information about the use of this flag. Identification (bit 21). The ability of a program or procedure to set or clear this flag indicates support for the CPUID instruction. VIP ID 2.4. MEMORY-MANAGEMENT REGISTERS The processor provides four memory-management registers (GDTR, LDTR, IDTR, and TR) that specify the locations of the data structures which control segmented memory management (refer to Figure 2-4). Special instructions are provided for loading and storing these registers. 47 GDTR IDTR System Table Registers 16 15 32-bit Linear Base Address 32-bit Linear Base Address 0 16-Bit Table Limit 16-Bit Table Limit System Segment 15 Registers 0 Task Register LDTR Seg. Sel. Seg. Sel. Segment Descriptor Registers (Automatically Loaded) Attributes 32-bit Linear Base Address 32-bit Linear Base Address Segment Limit Segment Limit Figure 2-4. Memory Management Registers 2.4.1. Global Descriptor Table Register (GDTR) The GDTR register holds the 32-bit base address and 16-bit table limit for the GDT. The base address specifies the linear address of byte 0 of the GDT; the table limit specifies the number of bytes in the table. The LGDT and SGDT instructions load and store the GDTR register, respectively. On power up or reset of the processor, the base address is set to the default value of 0 and 2-10 SYSTEM ARCHITECTURE OVERVIEW the limit is set to FFFFH. A new base address must be loaded into the GDTR as part of the processor initialization process for protected-mode operation. Refer to Section 3.5.1., “Segment Descriptor Tables” in Chapter 3, Protected-Mode Memory Management for more information on the base address and limit fields. 2.4.2. Local Descriptor Table Register (LDTR) The LDTR register holds the 16-bit segment selector, 32-bit base address, 16-bit segment limit, and descriptor attributes for the LDT. The base address specifies the linear address of byte 0 of the LDT segment; the segment limit specifies the number of bytes in the segment. Refer to Section 3.5.1., “Segment Descriptor Tables” in Chapter 3, Protected-Mode Memory Management for more information on the base address and limit fields. The LLDT and SLDT instructions load and store the segment selector part of the LDTR register, respectively. The segment that contains the LDT must have a segment descriptor in the GDT. When the LLDT instruction loads a segment selector in the LDTR, the base address, limit, and descriptor attributes from the LDT descriptor are automatically loaded into the LDTR. When a task switch occurs, the LDTR is automatically loaded with the segment selector and descriptor for the LDT for the new task. The contents of the LDTR are not automatically saved prior to writing the new LDT information into the register. On power up or reset of the processor, the segment selector and base address are set to the default value of 0 and the limit is set to FFFFH. 2.4.3. IDTR Interrupt Descriptor Table Register The IDTR register holds the 32-bit base address and 16-bit table limit for the IDT. The base address specifies the linear address of byte 0 of the IDT; the table limit specifies the number of bytes in the table. The LIDT and SIDT instructions load and store the IDTR register, respectively. On power up or reset of the processor, the base address is set to the default value of 0 and the limit is set to FFFFH. The base address and limit in the register can then be changed as part of the processor initialization process. Refer to Section 5.8., “Interrupt Descriptor Table (IDT)” in Chapter 5, Interrupt and Exception Handling for more information on the base address and limit fields. 2.4.4. Task Register (TR) The task register holds the 16-bit segment selector, 32-bit base address, 16-bit segment limit, and descriptor attributes for the TSS of the current task. It references a TSS descriptor in the GDT. The base a...
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

Ask a homework question - tutors are online