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Unformatted text preview: 523 524 525 526 527 592 600 601 616 617 618 619 620 621 622 623 767 Register Name MTRRphysBase3 MTRRphysMask3 MTRRphysBase4 MTRRphysMask4 MTRRphysBase5 MTRRphysMask5 MTRRphysBase6 MTRRphysMask6 MTRRphysBase7 MTRRphysMask7 MTRRfix64K_00000 MTRRfix16K_80000 MTRRfix16K_A0000 MTRRfix4K_C0000 MTRRfix4K_C8000 MTRRfix4K_D0000 MTRRfix4K_D8000 MTRRfix4K_E0000 MTRRfix4K_E8000 MTRRfix4K_F0000 MTRRfix4K_F8000 MTRRdefType 2:0 10 11 400H 401H 1024 1025 MC0_CTL MC0_STATUS 63 62 61 60 59 MC_STATUS_V MC_STATUS_O MC_STATUS_UC MC_STATUS_EN MC_STATUS_MISCV Default memory type Fixed MTRR enable MTRR Enable Bit Description B-8 MODEL-SPECIFIC REGISTERS Table B-1. Model-Specific Registers (MSRs) (Contd.)
Register Address Hex Dec 58 57 31:16 15:0 402H 403H 404H 405H 406H 407H 408H 409H 40AH 40BH 40CH 40DH 40EH 40FH 410H 411H 412H 413H 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 MC0_ADDR MC0_MISC MC1_CTL MC1_STATUS MC1_ADDR MC1_MISC MC2_CTL MC2_STATUS MC2_ADDR MC2_MISC MC4_CTL MC4_STATUS MC4_ADDR MC4_MISC MC3_CTL MC3_STATUS MC3_ADDR MC3_MISC Defined in MCA architecture but not implemented in the P6 family processors Bit definitions same as MC0_STATUS Bit definitions same as MC0_STATUS Defined in MCA architecture but not implemented in P6 Family processors Defined in MCA architecture but not implemented in the P6 family processors Defined in MCA architecture but not implemented in the P6 family processors Bit definitions same as MC0_STATUS Defined in MCA architecture but not implemented in the P6 family processors Bit definitions same as MC0_STATUS Defined in MCA architecture but not implemented in the P6 family processors Register Name Bit Description MC_STATUS_ADDRV MC_STATUS_DAM MC_STATUS_MCACOD MC_STATUS_MSCOD NOTES: 1. Bit 0 of this register has been redefined several times, and is no longer used in Pentium® Pro processors. 2. The processor number feature may be disabled by setting bit 21 of the BBL_CR_CTL MSR (model-specific register address 119h) to “1”. Once set, bit 21 of the BBL_CR_CTL may not be cleared. This bit is write-once. The processor number feature will be disabled until the processor is reset. 3. The Pentium® III processor will prevent FSB frequency overclocking with a new shutdown mechanism. If the FSB frequency selected is greater than the internal FSB frequency the processor will shutdown. If the FSB selected is less than the internal FSB frequency the BIOS may choose to use bit 11 to implement its own shutdown policy. B-9 C
Dual-Processor Bootup Sequence Example
(Specific to Pentium® Processors) APPENDIX C DUAL-PROCESSOR (DP) BOOTUP SEQUENCE EXAMPLE (SPECIFIC TO PENTIUM® PROCESSORS)
The following example shows the DP protocol for booting two Pentium® processors (a primary processor and a secondary processor) in a DP system and initializing their APICs. For dual-processor systems based on Pentium® processors, the APIC ID of the primary processor is always 0. The following constants and data definitions are used in the accompanying code examples. They are based on the addresses of the APIC registers as defined in Table 7-1 in Chapter 7. ICR_LOW ICR_HI SVR APIC_ID LVT3 APIC_ENABLED BOOT_ID UPGRD_ID EQU 0FEE00300H EQU 0FEE00310H EQU 0FEE000F0H EQU 0FEE00020H EQU 0FEE00370H EQU 100H DW ? DW ? C.1. PRIMARY PROCESSOR’S SEQUENCE OF EVENTS
1. The primary processor boots at the Intel Architecture address and executes until it is ready to activate the secondary processor. 2. Initialization software should execute the CPUID instruction to determine if the primary processor is a “GenuineIntel.” The values of EAX and EDX should be saved into a configuration RAM space for use later. If the type field (in the EAX register following CPUID instruction execution) is 01B in bits 13 and 14, respectively, the processor is a future Pentium® OverDrive® processor and the Pentium® processor (735/90, 815/100, 1000,120, 1110/133) has been put to sleep. This means the system is a uniprocessor system and normal AT system configuration can continue. Go to step 14 to configure the APIC. If the type field is 00B, the processor is the primary processor and detection of the secondary processor is required. Continue with steps 3 through 13. C-1 DUAL-PROCESSOR (DP) BOOTUP SEQUENCE EXAMPLE (SPECIFIC 3. The following operation can be used to detect the secondary processor: Set a timer before sending the start-up IPI to the secondary processor. In the secondary processor’s initialization routine, it should write a value into memory indicating its presence. The primary processor can then use the timer expiration to check if something has been written into memory. If the timer expires and nothing has been written into memory, the secondary processor is not present or some error has occurred. 4. Load start-up code for the secondary processor to execute into a 4-KByte page in the lower 1 MByte of memory. 5. Switch to protected mode (to access APIC address space above 1 MByte). 6. Determine the Pentium® processor’s APIC ID from the local APIC ID regist...
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