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Unformatted text preview: the RDMSR and WRMSR instructions, respectively. When performing software initialization of a Pentium® Pro or Pentium® processor, many of the MSRs will need to be initialized to set up things like performance-monitoring events, run-time machine checks, and memory types for physical memory. Systems configured to implement FRC mode must write all of the processors’ internal MSRs to deterministic values before performing either a read or read-modify-write operation using these registers. The following is a list of MSRs that are not initialized by the processors’ reset sequences. • • • • All fixed and variable MTRRs. All Machine Check Architecture (MCA) status registers. Microcode update signature register. All L2 cache initialization MSRs. The list of available performance-monitoring counters for the Pentium® Pro and Pentium® processors is given in Appendix A, Performance-Monitoring Events, and the list of available MSRs for the Pentium® Pro processor is given in Appendix B, Model-Specific Registers. The references earlier in this section show where the functions of the various groups of MSRs are described in this manual. 8.5. MEMORY TYPE RANGE REGISTERS (MTRRS) Memory type range registers (MTRRs) were introduced into the Intel Architecture with the Pentium® Pro processor. They allow the type of caching (or no caching) to be specified in system memory for selected physical address ranges. They allow memory accesses to be optimized for various types of memory such as RAM, ROM, frame buffer memory, and memory-mapped I/O devices. In general, initializing the MTRRs is normally handled by the software initialization code or BIOS and is not an operating system or executive function. At the very least, all the MTRRs must be cleared to 0, which selects the uncached (UC) memory type. Refer to Section 9.12., 8-9 PROCESSOR MANAGEMENT AND INITIALIZATION “Memory Type Range Registers (MTRRs)”, in Chapter 9, Memory Cache Control, for detailed information on the MTRRs. 8.6. SOFTWARE INITIALIZATION FOR REAL-ADDRESS MODE OPERATION Following a hardware reset (either through a power-up or the assertion of the RESET# pin) the processor is placed in real-address mode and begins executing software initialization code from physical address FFFFFFF0H. Software initialization code must first set up the necessary data structures for handling basic system functions, such as a real-mode IDT for handling interrupts and exceptions. If the processor is to remain in real-address mode, software must then load additional operating-system or executive code modules and data structures to allow reliable execution of application programs in real-address mode. If the processor is going to operate in protected mode, software must load the necessary data structures to operate in protected mode and then switch to protected mode. The protected-mode data structures that must be loaded are described in Section 8.7., “Software Initialization for Protected-Mode Operation”. 8.6.1. Real-Address Mode IDT In real-address mode, the only system data structure that must be loaded into memory is the IDT (also called the “interrupt vector table”). By default, the address of the base of the IDT is physical address 0H. This address can be changed by using the LIDT instruction to change the base address value in the IDTR. Software initialization code needs to load interrupt- and exceptionhandler pointers into the IDT before interrupts can be enabled. The actual interrupt- and exception-handler code can be contained either in EPROM or RAM; however, the code must be located within the 1-MByte addressable range of the processor in real-address mode. If the handler code is to be stored in RAM, it must be loaded along with the IDT. 8.6.2. NMI Interrupt Handling The NMI interrupt is always enabled (except when multiple NMIs are nested). If the IDT and the NMI interrupt handler need to be loaded into RAM, there will be a period of time following hardware reset when an NMI interrupt cannot be handled. During this time, hardware must provide a mechanism to prevent an NMI interrupt from halting code execution until the IDT and the necessary NMI handler software is loaded. 8-10 PROCESSOR MANAGEMENT AND INITIALIZATION Here are two examples of how NMIs can be handled during the initial states of processor initialization: • • A simple IDT and NMI interrupt handler can be provided in EPROM. This allows an NMI interrupt to be handled immediately after reset initialization. The system hardware can provide a mechanism to enable and disable NMIs by passing the NMI# signal through an AND gate controlled by a flag in an I/O port. Hardware can clear the flag when the processor is reset, and software can set the flag when it is ready to handle NMI interrupts. 8.7. SOFTWARE INITIALIZATION FOR PROTECTED-MODE OPERATION The processor is placed in real-address mode following a hardware reset. At this point in the initialization process, some basic data structures and code module...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10