Stack instructions push and pop to general purpose

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Unformatted text preview: -2). The interrupt table (which has 4-byte entries) takes the place of the interrupt descriptor table (IDT, with 8-byte entries) used when handling protected-mode interrupts and exceptions. Interrupt and exception vector numbers provide an index to entries in the interrupt table. Each entry provides a pointer (called a “vector”) to an interrupt- or exception-handling procedure. Refer to • • • • • • • • 16-2 8086 EMULATION Section 16.1.4., “Interrupt and Exception Handling” for more details. It is possible for software to relocate the IDT by means of the LIDT instruction on Intel Architecture processors beginning with the Intel386™ processor. • The floating-point unit (FPU) is active and available to execute FPU instructions in realaddress mode. Programs written to run on the Intel 8087 and Intel 287 math coprocessors can be run in real-address mode without modification. The following extensions to the Intel 8086 execution environment are available in the Intel Architecture’s real-address mode. If backwards compatibility to Intel 286 and Intel 8086 processors is required, these features should not be used in new programs written to run in real-address mode. • • • • Two additional segment registers (FS and GS) are available. Many of the integer and system instructions that have been added to P6-family processors can be executed in real-address mode (refer to Section 16.1.3., “Instructions Supported in Real-Address Mode”). The 32-bit operand prefix can be used in real-address mode programs to execute the 32-bit forms of instructions. This prefix also allows real-address mode programs to use the processor’s 32-bit general-purpose registers. The 32-bit address prefix can be used in real-address mode programs, allowing 32-bit offsets. The following sections describe address formation, registers, available instructions, and interrupt and exception handling in real-address mode. For information on I/O in real-address mode, refer to Chapter 9, Input/Output, in the Intel Architecture Software Developer’s Manual, Volume 1. 16.1.1. Address Translation in Real-Address Mode In real-address mode, the processor does not interpret segment selectors as indexes into a descriptor table; instead, it uses them directly to form linear addresses as the 8086 processor does. It shifts the segment selector left by 4 bits to form a 20-bit base address (refer to Figure 16-1). The offset into a segment is added to the base address to create a linear address that maps directly to the physical address space. When using 8086-style address translation, it is possible to specify addresses larger than 1 MByte. For example, with a segment selector value of FFFFH and an offset of FFFFH, the linear (and physical) address would be 10FFEFH (1 megabyte plus 64 KBytes). The 8086 processor, which can form addresses only up to 20 bits long, truncates the high-order bit, thereby “wrapping” this address to FFEFH. When operating in real-address mode, however, the processor does not truncate such an address and uses it as a physical address. (Note, however, that for Intel Architecture processors beginning with the Intel486™ processor, the A20M# signal can be used in real-address mode to mask address line A20, thereby mimicking the 20-bit wrap-around behavior of the 8086 processor.) Care should be take to ensure that A20M# based address wrapping is handled correctly in multiprocessor based system. 16-3 8086 EMULATION 19 43 0 Base 16-bit Segment Selector 19 16 15 0000 0 + Offset 0000 16-bit Effective Address = Linear Address 19 0 20-bit Linear Address Figure 16-1. Real-Address Mode Address Translation The Intel Architecture processors beginning with the Intel386™ processor can generate 32-bit offsets using an address override prefix; however, in real-address mode, the value of a 32-bit offset may not exceed FFFFH without causing an exception. For full compatibility with Intel 286 real-address mode, pseudo-protection faults (interrupt 12 or 13) occur if a 32-bit offset is generated outside the range 0 through FFFFH. 16.1.2. Registers Supported in Real-Address Mode The register set available in real-address mode includes all the registers defined for the 8086 processor plus the new registers introduced inP6-family processors, such as the FS and GS segment registers, the debug registers, the control registers, and the floating-point unit registers. The 32-bit operand prefix allows a real-address mode program to use the 32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESP, EBP, ESI, and EDI). 16.1.3. Instructions Supported in Real-Address Mode The following instructions make up the core instruction set for the 8086 processor. If backwards compatibility to the Intel 286 and Intel 8086 processors is required, only these instructions should be used in a new program written to run in real-address mode. • • • • • 16-4 Move (MOV) instructions that move operands between general-purpose registers, segment registers, and between memory and general-purpose registers, The exchange (XCHG) instruction. Load...
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