IntelSoftwareDevelopersManual

Stores the idt base address and limit from the idtr

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Unformatted text preview: technology. 5. This instruction was introduced into the Intel Architecture with the Pentium® III processor. 2-19 SYSTEM ARCHITECTURE OVERVIEW 2.6.1. Loading and Storing System Registers The GDTR, LDTR, IDTR, and TR registers each have a load and store instruction for loading data into and storing data from the register: LGDT (Load GDTR Register) Loads the GDT base address and limit from memory into the GDTR register. SGDT (Store GDTR Register) Stores the GDT base address and limit from the GDTR register into memory. LIDT (Load IDTR Register) SIDT (Load IDTR Register LLDT (Load LDT Register) Loads the IDT base address and limit from memory into the IDTR register. Stores the IDT base address and limit from the IDTR register into memory. Loads the LDT segment selector and segment descriptor from memory into the LDTR. (The segment selector operand can also be located in a general-purpose register.) Stores the LDT segment selector from the LDTR register into memory or a general-purpose register. Loads segment selector and segment descriptor for a TSS from memory into the task register. (The segment selector operand can also be located in a general-purpose register.) Stores the segment selector for the current task TSS from the task register into memory or a general-purpose register. SLDT (Store LDT Register) LTR (Load Task Register) STR (Store Task Register) The LMSW (load machine status word) and SMSW (store machine status word) instructions operate on bits 0 through 15 of control register CR0. These instructions are provided for compatibility with the 16-bit Intel 286 processor. Program written to run on 32-bit Intel Architecture processors should not use these instructions. Instead, they should access the control register CR0 using the MOV instruction. The CLTS (clear TS flag in CR0) instruction is provided for use in handling a device-not-available exception (#NM) that occurs when the processor attempts to execute a floating-point instruction when the TS flag is set. This instruction allows the TS flag to be cleared after the FPU context has been saved, preventing further #NM exceptions. Refer to Section 2.5., “Control Registers” for more information about the TS flag. The control registers (CR0, CR1, CR2, CR3, and CR4) are loaded with the MOV instruction. This instruction can load a control register from a general-purpose register or store the contents of the control register in a general-purpose register. 2.6.2. Verifying of Access Privileges The processor provides several instructions for examining segment selectors and segment descriptors to determine if access to their associated segments is allowed. These instructions 2-20 SYSTEM ARCHITECTURE OVERVIEW duplicate some of the automatic access rights and type checking done by the processor, thus allowing operating-system or executive software to prevent exceptions from being generated. The ARPL (adjust RPL) instruction adjusts the RPL (requestor privilege level) of a segment selector to match that of the program or procedure that supplied the segment selector. Refer to Section 4.10.4., “Checking Caller Access Privileges (ARPL Instruction)” in Chapter 4, Protection for a detailed explanation of the function and use of this instruction. The LAR (load access rights) instruction verifies the accessibility of a specified segment and loads the access rights information from the segment’s segment descriptor into a generalpurpose register. Software can then examine the access rights to determine if the segment type is compatible with its intended use. Refer to Section 4.10.1., “Checking Access Rights (LAR Instruction)” in Chapter 4, Protection for a detailed explanation of the function and use of this instruction. The LSL (load segment limit) instruction verifies the accessibility of a specified segment and loads the segment limit from the segment’s segment descriptor into a general-purpose register. Software can then compare the segment limit with an offset into the segment to determine whether the offset lies within the segment. Refer to Section 4.10.3., “Checking That the Pointer Offset Is Within Limits (LSL Instruction)” in Chapter 4, Protection for a detailed explanation of the function and use of this instruction. The VERR (verify for reading) and VERW (verify for writing) instructions verify if a selected segment is readable or writable, respectively, at the CPL. Refer to Section 4.10.2., “Checking Read/Write Rights (VERR and VERW Instructions)” in Chapter 4, Protection for a detailed explanation of the function and use of this instruction. 2.6.3. Loading and Storing Debug Registers The internal debugging facilities in the processor are controlled by a set of 8 debug registers (DR0 through DR7). The MOV instruction allows setup data to be loaded into and stored from these registers. 2.6.4. Invalidating Caches and TLBs The processor provides several instructions for use in explicitly invalidating its caches and TLB entries. The INVD (invalidate cache wi...
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