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Unformatted text preview: e number. An update block is considered unused and available for storing a new update if its header version contains the value 0FFFFFFFFh after return from this function call. The actual implementation of NVRAM storage management is not specified here and is BIOS dependent. As an example, the actual data value used to represent an empty block by the BIOS may be zero, rather than 8-49 PROCESSOR MANAGEMENT AND INITIALIZATION 0FFFFFFFFh. The BIOS is responsible for translating this information into the header provided by this function. 188.8.131.52. RETURN CODES After the call has been made, the return codes listed in Table 8-8 are available in the AH register.
Table 8-14. Return Code Definitions
Return Code SUCCESS NOT_IMPLEMENTED ERASE_FAILURE WRITE_FAILURE READ_FAILURE STORAGE_FULL Value 00h 86h 90h 91h 92h 93h Description Function completed successfully Function not implemented A failure because of the inability to erase the storage device A failure because of the inability to write the storage device A failure because of the inability to read the storage device The BIOS non-volatile storage area is unable to accommodate the update because all available update blocks are filled with updates that are needed for processors in the system The processor stepping does not currently exist in the system The update header contains a header or loader version that is not recognized by the BIOS The update does not checksum correctly The update was rejected by the processor The same or more recent revision of the update exists in the storage device The update number exceeds the maximum number of update blocks implemented by the BIOS CPU_NOT_PRESENT INVALID_HEADER INVALID_HEADER_CS SECURITY_FAILURE INVALID_REVISION UPDATE_NUM_INVALID 94h 95h 96h 97h 98h 99h 8-50 9
Memory Cache Control MEMORY CACHE CONTROL CHAPTER 9 MEMORY CACHE CONTROL
This chapter describes the Intel Architecture’s memory cache and cache control mechanisms, the TLBs, and the write buffer. It also describes the memory type range registers (MTRRs) found in the P6 family processors and how they are used to control caching of physical memory locations. 9.1. INTERNAL CACHES, TLBS, AND BUFFERS The Intel Architecture supports caches, translation look aside buffers (TLBs), and write buffers for temporary on-chip (and external) storage of instructions and data (see Figure 9-1). Table 9-1 shows the characteristics of these caches and buffers for the P6 family, Pentium®, and Intel486™ processors. The sizes and characteristics of these units are machine specific and may change in future versions of the processor. The CPUID instruction returns the sizes and characteristics of the caches and buffers for the processor on which the instruction is executed. For more information, see “CPUID—CPU Identification” in Chapter 3 of the Intel Architecture Software Developer’s Manual, Volume 2. 9-1 MEMORY CACHE CONTROL Physical Memory L2 Cache2,3 Cache Bus Inst. TLBs Bus Interface Unit Data TLBs Data Cache Unit (L11) System Bus (External) Instruction Fetch Unit
1 Instruction Cache (L11) Write Buffer For the Intel486™ processor, the L1 Cache is a unified instruction and data cache. For the Pentium® and Intel486™ processors, the L2 Cache is external to the processor package and there is no cache bus (that is, the L2 cache interfaces with the system bus). For the Pentium® Pro, Pentium® II and Pentium® III processors, the L2 Cache is internal to the processor package and there is a separate cache bus. 2 3 Figure 9-1. Intel Architecture Caches The Intel Architecture defines two separate caches: the level 1 (L1) cache and the level 2 (L2) cache (see Figure 9-1). The L1 cache is closely coupled to the instruction fetch unit and execution units of the processor. For the Pentium® and P6 family processors, the L1 cache is divided into two sections: one dedicated to caching instructions and one to caching data. For the Intel486™ processor, the L1 cache is a unified instruction and data cache. 9-2 MEMORY CACHE CONTROL Table 9-1. Characteristics of the Caches, TLBs, and Write Buffer in Intel Architecture Processors
Cache or Buffer L1 Instruction Cache1
® Characteristics - P6 family and Pentium processors: 8 or 16 KBytes, 4-way set associative, 32-byte cache line size; 2-way set associative for earlier Pentium® processors. - Intel486™ processor: 8 or 16 KBytes, 4-way set associative, 16-byte cache line size, instruction and data cache combined. - P6 family processors: 16 KBytes, 4-way set associative, 32-byte cache line size; 8 KBytes, 2-way set associative for earlier P6 family processors. - Pentium® processors: 16 KBytes, 4-way set associative, 32-byte cache line size; 8 KBytes, 2-way set associative for earlier Pentium® processors. - Intel486™ processor: (see L1 instruction cache). - P6 family processors: 128 KBytes, 256 KBytes, 512 KBytes, 1 MByte, or 2 MByte, 4-way set associative, 32-byte cache line size. - Pentium® processor: System specific, typically 256 or 512 KBytes, 4-way set associative...
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