IntelSoftwareDevelopersManual

The apr address is fee0 0090h and its value after

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Unformatted text preview: s the TPR value is decreased enough to allow that. This enables the operating system to block temporarily specific interrupts (generally low priority) from disturbing high-priority tasks execution. The priority threshold mechanism is not applicable for delivery modes excluding the vector information (that is, for ExtINT, NMI, SMI, INIT, INIT-Deassert, and Start-Up delivery modes). 7-31 MULTIPLE-PROCESSOR MANAGEMENT 31 87 0 Reserved Address: FEE0 0080H Value after reset: 0H Task Priority Figure 7-12. Task Priority Register (TPR) The Task Priority is specified in the TPR. The 4 most-significant bits of the task priority correspond to the 16 interrupt priorities, while the 4 least-significant bits correspond to the sub-class priority. The TPR value is generally denoted as x:y, where x is the main priority and y provides more precision within a given priority class. When the x-value of the TPR is 15, the APIC will not accept any interrupts. 7.5.13.3. PROCESSOR PRIORITY REGISTER (PPR) The processor priority register (PPR) is used to determine whether a pending interrupt can be dispensed to the processor. Its value is computed as follows: IF TPR[7:4] ≥ ISRV[7:4] THEN PPR[7:0] = TPR[7:0] ELSE PPR[7:4] = ISRV[7:4] AND PPR[3:0] = 0 Where ISRV is the vector of the highest priority ISR bit set, or zero if no ISR bit is set. The PPR format is identical to that of the TPR. The PPR address is FEE000A0H, and its value after reset is zero. 7.5.13.4. ARBITRATION PRIORITY REGISTER (APR) Arbitration priority register (APR) holds the current, lowest-priority of the processor, a value used during lowest priority arbitration (refer to Section 7.5.16., “APIC Bus Arbitration Mechanism and Protocol”). The APR format is identical to that of the TPR. The APR value is computed as the following. IF (TPR[7:4] ≥ IRRV[7:4]) AND (TPR[7:4] > ISRV[7:4]) THEN APR[7:0] = TPR[7:0] ELSE APR[7:4] = max(TPR[7:4] AND ISRV[7:4], IRRV[7:4]), APR[3:0]=0. Here, IRRV is the interrupt vector with the highest priority IRR bit set or cleared (if no IRR bit is set). The APR address is FEE0 0090H, and its value after reset is 0. 7-32 MULTIPLE-PROCESSOR MANAGEMENT 7.5.13.5. SPURIOUS INTERRUPT A special situation may occur when a processor raises its task priority to be greater than or equal to the level of the interrupt for which the processor INTR signal is currently being asserted. If at the time the INTA cycle is issued, the interrupt that was to be dispensed has become masked (programmed by software), the local APIC will return a spurious-interrupt vector to the processor. Dispensing the spurious-interrupt vector does not affect the ISR, so the handler for this vector should return without an EOI. 7.5.13.6. END-OF-INTERRUPT (EOI) During the interrupt serving routine, software should indicate acceptance of lowest-priority, fixed, timer, and error interrupts by writing an arbitrary value into its local APIC end-of-interrupt (EOI) register (refer to Figure 7-13). This is an indication for the local APIC it can issue the next interrupt, regardless of whether the current interrupt service has been terminated or not. Note that interrupts whose priority is higher than that currently in service, do not wait for the EOI command corresponding to the interrupt in service. 31 0 Address: 0FEE0 00B0H Value after reset: 0H Figure 7-13. EOI Register Upon receiving end-of-interrupt, the APIC clears the highest priority bit in the ISR and selects the next highest priority interrupt for posting to the CPU. If the terminated interrupt was a leveltriggered interrupt, the local APIC sends an end-of-interrupt message to all I/O APICs. Note that EOI command is supplied for the above two interrupt delivery modes regardless of the interrupt source (that is, as a result of either the I/O APIC interrupts or those issued on local pins or using the ICR). For future compatibility, the software is requested to issue the end-of-interrupt command by writing a value of 0H into the EOI register. 7.5.14. Local APIC State In P6 family processors, all local APICs are initialized in a software-disabled state after powerup. A software-disabled local APIC unit responds only to self-interrupts and to INIT, NMI, SMI, and start-up messages arriving on the APIC Bus. The operation of local APICs during the disabled state is as follows: • For the INIT, NMI, SMI, and start-up messages, the APIC behaves normally, as if fully enabled. 7-33 MULTIPLE-PROCESSOR MANAGEMENT • • • • • Pending interrupts in the IRR and ISR registers are held and require masking or handling by the CPU. A disabled local APIC does not affect the sending of APIC messages. It is software’s responsibility to avoid issuing ICR commands if no sending of interrupts is desired. Disabling a local APIC does not affect the message in progress. The local APIC will complete the reception/transmission of the current message and then enter the disabled state. A disabled local APIC automatically sets all mask bits in the LVT entries. Trying to reset these bits in the local vector table will be...
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