The intel architecture provides a mechanism for

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Unformatted text preview: ed, and a Streaming SIMD Extensions instruction was executed, then no exception is raised. 5-54 INTERRUPT AND EXCEPTION HANDLING Interrupts 32 to 255—User Defined Interrupts Exception Class Description Indicates that the processor did one of the following things: Not applicable. • • Executed an INT n instruction where the instruction operand is one of the vector numbers from 32 through 255. Responded to an interrupt request at the INTR pin or from the local APIC when the interrupt vector number associated with the request is from 32 through 255. Exception Error Code Not applicable. Saved Instruction Pointer The saved contents of CS and EIP registers point to the instruction that follows the INT n instruction or instruction following the instruction on which the INTR signal occurred. Program State Change A program-state change does not accompany interrupts generated by the INT n instruction or the INTR signal. The INT n instruction generates the interrupt within the instruction stream. When the processor receives an INTR signal, it commits all state changes for all previous instructions before it responds to the interrupt; so, program execution can resume upon returning from the interrupt handler. 5-55 INTERRUPT AND EXCEPTION HANDLING 5-56 6 Task Management TASK MANAGEMENT CHAPTER 6 TASK MANAGEMENT This chapter describes the Intel Architecture’s task management facilities. These facilities are only available when the processor is running in protected mode. 6.1. TASK MANAGEMENT OVERVIEW A task is a unit of work that a processor can dispatch, execute, and suspend. It can be used to execute a program, a task or process, an operating-system service utility, an interrupt or exception handler, or a kernel or executive utility. The Intel Architecture provides a mechanism for saving the state of a task, for dispatching tasks for execution, and for switching from one task to another. When operating in protected mode, all processor execution takes place from within a task. Even simple systems must define at least one task. More complex systems can use the processor’s task management facilities to support multitasking applications. 6.1.1. Task Structure A task is made up of two parts: a task execution space and a task-state segment (TSS). The task execution space consists of a code segment, a stack segment, and one or more data segments (refer to Figure 6-1). If an operating system or executive uses the processor’s privilege-level protection mechanism, the task execution space also provides a separate stack for each privilege level. The TSS specifies the segments that make up the task execution space and provides a storage place for task state information. In multitasking systems, the TSS also provides a mechanism for linking tasks. NOTE This chapter describes primarily 32-bit tasks and the 32-bit TSS structure. For information on 16-bit tasks and the 16-bit TSS structure, refer to Section 6.6., “16-Bit Task-State Segment (TSS)”. A task is identified by the segment selector for its TSS. When a task is loaded into the processor for execution, the segment selector, base address, limit, and segment descriptor attributes for the TSS are loaded into the task register (refer to Section 2.4.4., “Task Register (TR)” in Chapter 2, System Architecture Overview). If paging is implemented for the task, the base address of the page directory used by the task is loaded into control register CR3. 6-1 TASK MANAGEMENT Code Segment Task-State Segment (TSS) Data Segment Stack Segment (Current Priv. Level) Stack Seg. Priv. Level 0 Stack Seg. Priv. Level 1 Task Register CR3 Stack Segment (Priv. Level 2) Figure 6-1. Structure of a Task 6.1.2. Task State The following items define the state of the currently executing task: • • • • • • • • • • The task’s current execution space, defined by the segment selectors in the segment registers (CS, DS, SS, ES, FS, and GS). The state of the general-purpose registers. The state of the EFLAGS register. The state of the EIP register. The state of control register CR3. The state of the task register. The state of the LDTR register. The I/O map base address and I/O map (contained in the TSS). Stack pointers to the privilege 0, 1, and 2 stacks (contained in the TSS). Link to previously executed task (contained in the TSS). Prior to dispatching a task, all of these items are contained in the task’s TSS, except the state of the task register. Also, the complete contents of the LDTR register are not contained in the TSS, only the segment selector for the LDT. 6-2 TASK MANAGEMENT 6.1.3. Executing a Task Software or the processor can dispatch a task for execution in one of the following ways: • • • • • A explicit call to a task with the CALL instruction. A explicit jump to a task with the JMP instruction. An implicit call (by the processor) to an interrupt-handler task. An implicit call to an exception-handler task. A return (initiated with an IRET instruction) when the NT flag in the EFLAGS register is set. All of these methods of dispatching a task identify the task to be dispatched with a segment selec...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

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