Unformatted text preview: are implementation specific for the Pentium® processor. These MSRs can be read with the RDMSR instruction. Refer to Table B-1 in Appendix B, Model-Specific Registers for the register addresses for these MSRs. The machine-check error reporting mechanism that the Pentium ® processors use is similar to that used in the P6 family processors. That is, when an error is detected, it is recorded in the P5_MC_TYPE and P5_MC_ADDR MSRs and then the processor generates a machine-check exception (#MC). Refer to Section 13.3.3., “Mapping of the Pentium® Processor Machine-Check Errors to the P6 Family Machine-Check Architecture” and Section 13.7.2., “Pentium® Processor MachineCheck Exception Handling” for information on compatibility between machine-check code written to run on the Pentium® processors and code written to run on P6 family processors. 13-1 MACHINE-CHECK ARCHITECTURE 13.3. MACHINE-CHECK MSRS
The machine check MSRs in the P6 family processors consist of a set of global control and status registers and several error-reporting register banks (refer to Figure 13-1). Each errorreporting bank is associated with a specific hardware unit (or group of hardware units) within the processor. The RDMSR and WRMSR instructions are used to read and write these registers. Global Control Registers 63 MCG_CAP Register 63 MCG_STATUS Register 63 MCG_CTL Register* * Not present in the Pentium® Pro processor. 63 0 63 0 63 0 63 Error-Reporting Bank Registers (One Set for Each Hardware Unit) 0 MCi_CTL Register 0 MCi_STATUS Register 0 MCi_ADDR Register 0 MCi_MISC Register Figure 13-1. Machine-Check MSRs 13.3.1. Machine-Check Global Control MSRs
The machine-check global control registers include the MCG_CAP, MCG_STATUS, and MCG_CTL MSRs. Refer to Appendix B, Model-Specific Registers for the addresses of these registers. 184.108.40.206. MCG_CAP MSR The MCG_CAP MSR is a read-only register that provides information about the machine-check architecture implementation in the processor (refer to Figure 13-2). It contains the following field and flag: Count field, bits 0 through 7 Indicates the number of hardware unit error-reporting banks available in a particular processor implementation. MCG_CTL_P (register present) flag, bit 8 Indicates that the MCG_CTL register is present when set, and absent when clear. Bits 9 through 63 are reserved. The effect of writing to the MCG_CAP register is undefined. Figure 5-1 shows the bit fields of MCG_CAP. 13-2 MACHINE-CHECK ARCHITECTURE 63 98 7 0 Reserved MCG_CTL_P—MCG_CTL register present Count—Number of reporting banks Count Figure 13-2. MCG_CAP Register 220.127.116.11. MCG_STATUS MSR The MCG_STATUS MSR describes the current state of the processor after a machine-check exception has occurred (refer to Figure 13-3). This register contains the following flags: RIPV (restart IP valid) flag, bit 0 Indicates (when set) that program execution can be restarted reliably at the instruction pointed to by the instruction pointer pushed on the stack when the machine-check exception is generated. When clear, the program cannot be reliably restarted at the pushed instruction pointer. EIPV (error IP valid) flag, bit 1 Indicates (when set) that the instruction pointed to by the instruction pointer pushed onto the stack when the machine-check exception is generated is directly associated with the error. When this flag is cleared, the instruction pointed to may not be associated with the error. MCIP (machine check in progress) flag, bit 2 Indicates (when set) that a machine-check exception was generated. Software can set or clear this flag. The occurrence of a second Machine-Check Event while MCIP is set will cause the processor to enter a shutdown state. Bits 3 through 63 in the MCG_STATUS register are reserved. 63 3210 Reserved M C I P ER II PP VV MCIP—Machine check in progress flag EIPV—Error IP valid flag RIPV—Restart IP valid flag Figure 13-3. MCG_STATUS Register 13-3 MACHINE-CHECK ARCHITECTURE 18.104.22.168. MCG_CTL MSR The MCG_CTL register is present if the capability flag MCG_CTL_P is set in the MCG_CAP register. The MCG_CTL register controls the reporting of machine-check exceptions. If present (MCG_CTL_P flag in the MCG_CAP register is set), writing all 1s to this register enables all machine-check features and writing all 0s disables all machine-check features. All other values are undefined and/or implementation specific. 13.3.2. Error-Reporting Register Banks
Each error-reporting register bank can contains an MCi_CTL, MCi_STATUS, MCi_ADDR, and MCi_MISC MSR. The P6 family processors provide five banks of error-reporting registers. The first error-reporting register (MC0_CTL) always starts at address 400H. Refer to Table B-1 in Appendix B, Model-Specific Registers for the addresses of the other error-reporting registers. 22.214.171.124. MCi_CTL MSR The MCi_CTL MSR controls error reporting for specific errors produced by a particular hardware unit (or group of hardware units). Each of the 64 flags (EEj) represents a potential error. Setting an EEj flag enab...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10