IntelSoftwareDevelopersManual

The pwt flag enables write back caching of the page

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: processors.) Strict memory ordering is not enforced unless the MTRRs are disabled and/or all memory is referenced as uncached. For more information, see Section 7.2.4., “Strengthening or Weakening the Memory Ordering Model”. - Invalidation is inhibited when snooping; but is allowed with INVD and WBINVD instructions. - External snoop traffic is supported. L1 Yes Yes Yes Yes Yes Yes Yes Yes NA Yes Yes NA L21 Yes Yes Yes Yes 0 1 1 0 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1 1 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes NOTE: 1. The P6 family processors are the only Intel Architecture processors that contain an integrated L2 cache. The L2 column in this table is definitive for the P6 family processors. It is intended to represent what could be implemented in a Pentium® processor based system with a platform specific write-back L2 cache. 9-11 MEMORY CACHE CONTROL • NW flag, bit 29 of control register CR0—Controls the write policy for system memory locations. For more information, see Section 2.5., “Control Registers”, in Chapter 2, System Architecture Overview. If the NW and CD flags are clear, write-back is enabled for the whole of system memory (write-through for the Intel486™ processor), but may be restricted for individual pages or regions of memory by other cache-control mechanisms. Table 9-4 shows how the other combinations of CD and NW flags affects caching. NOTE For the Pentium processor, when the L1 cache is disabled (the CD and NW flags in control register CR0 are set), external snoops are accepted in DP (dual-processor) systems and inhibited in uniprocessor systems. When snoops are inhibited, address parity is not checked and APCHK# is not asserted for a corrupt address; however, when snoops are accepted, address parity is checked and APCHK# is asserted for corrupt addresses. ® • PCD flag in the page-directory and page-table entries—Controls caching for individual page tables and pages, respectively. For more information, see Section 3.6.4., “PageDirectory and Page-Table Entries”, in Chapter 3, Protected-Mode Memory Management. This flag only has effect when paging is enabled and the CD flag in control register CR0 is clear. The PCD flag enables caching of the page table or page when clear and prevents caching when set. PWT flag in the page-directory and page-table entries—Controls the write policy for individual page tables and pages, respectively. For more information, see Section 3.6.4., “Page-Directory and Page-Table Entries”, in Chapter 3, Protected-Mode Memory Management. This flag only has effect when paging is enabled and the NW flag in control register CR0 is clear. The PWT flag enables write-back caching of the page table or page when clear and write-through caching when set. PCD and PWT flags in control register CR3. Control the global caching and write policy for the page directory. For more information, see Section 2.5., “Control Registers”, in Chapter 2, System Architecture Overview. The PCD flag enables caching of the page directory when clear and prevents caching when set. The PWT flag enables write-back caching of the page directory when clear and write-through caching when set. These flags do not affect the caching and write policy for individual page tables. These flags only have effect when paging is enabled and the CD flag in control register CR0 is clear. G (global) flag in the page-directory and page-table entries (introduced to the Intel Architecture in the P6 family processors)—Controls the flushing of TLB entries for individual pages. See Section 3.7., “Translation Lookaside Buffers (TLBs)”, in Chapter 3, ProtectedMode Memory Management, for more information about this flag. PGE (page global enable) flag in control register CR4—Enables the establishment of global pages with the G flag. See Section 3.7., “Translation Lookaside Buffers (TLBs)”, in Chapter 3, Protected-Mode Memory Management, for more information about this flag. Memory type range registers (MTRRs) (introduced in the P6 family processors)—Control the type of caching used in specific regions of physical memory. Any of the caching types described in Section 9.3., “Methods of Caching Available”, can be selected. See Section • • • • • 9-12 MEMORY CACHE CONTROL 9.12., “Memory Type Range Registers (MTRRs)”, for a detailed description of the MTRRs. • KEN# and WB/WT# pins on Pentium® processor and KEN# pin alone on the Intel486™ processor—These pins allow external hardware to control the caching method used for specific areas of memory. They perform similar (but not identical) functions to the MTRRs in the P6 family processors. PCD and PWT pins on the Pentium® and Intel486™ processors—These pins (which are associated with the PCD and PWT flags in control register CR3 and in the page-directory and page-table entries) permit caching in an external L2 cache to be controlled on a pageby-page basis, consistent with the control exercised on the L1...
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

Ask a homework question - tutors are online