The tlbs satisfy most requests for reading the

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Unformatted text preview: s into the physical address space and to generate page-fault exceptions (when necessary) is contained in page directories and page tables stored in memory. Paging is different from segmentation through its use of fixed-size pages. Unlike segments, which usually are the same size as the code or data structures they hold, pages have a fixed size. If segmentation is the only form of address translation used, a data structure present in physical memory will have all of its parts in memory. If paging is used, a data structure can be partly in memory and partly in disk storage. To minimize the number of bus cycles required for address translation, the most recently accessed page-directory and page-table entries are cached in the processor in devices called translation lookaside buffers (TLBs). The TLBs satisfy most requests for reading the current page directory and page tables without requiring a bus cycle. Extra bus cycles occur only when the TLBs do not contain a page-table entry, which typically happens when a page has not been accessed for a long time. Refer to Section 3.7., “Translation Lookaside Buffers (TLBs)” for more information on the TLBs. 3.6.1. Paging Options Paging is controlled by three flags in the processor’s control registers: • • • PG (paging) flag, bit 31 of CR0 (available in all Intel Architecture processors beginning with the Intel386™ processor). PSE (page size extensions) flag, bit 4 of CR4 (introduced in the Pentium® and Pentium® Pro processors). PAE (physical address extension) flag, bit 5 of CR4 (introduced in the Pentium® Pro processors). The PG flag enables the page-translation mechanism. The operating system or executive usually sets this flag during processor initialization. The PG flag must be set if the processor’s pagetranslation mechanism is to be used to implement a demand-paged virtual memory system or if the operating system is designed to run more than one program (or task) in virtual-8086 mode. The PSE flag enables large page sizes: 4-MByte pages or 2-MByte pages (when the PAE flag is set). When the PSE flag is clear, the more common page length of 4 KBytes is used. Refer to Chapter, Linear Address Translation (4-MByte Pages) and Section 3.8.2., “Linear Address Translation With Extended Addressing Enabled (2-MByte or 4-MByte Pages)” for more information about the use of the PSE flag. The PAE flag enables 36-bit physical addresses. This physical address extension can only be used when paging is enabled. It relies on page directories and page tables to reference physical addresses above FFFFFFFFH. Refer to Section 3.8., “Physical Address Extension” for more information about the physical address extension. 3-19 PROTECTED-MODE MEMORY MANAGEMENT 3.6.2. Page Tables and Directories The information that the processor uses to translate linear addresses into physical addresses (when paging is enabled) is contained in four data structures: • • Page directory—An array of 32-bit page-directory entries (PDEs) contained in a 4-KByte page. Up to 1024 page-directory entries can be held in a page directory. Page table—An array of 32-bit page-table entries (PTEs) contained in a 4-KByte page. Up to 1024 page-table entries can be held in a page table. (Page tables are not used for 2MByte or 4-MByte pages. These page sizes are mapped directly from one or more pagedirectory entries.) Page—A 4-KByte, 2-MByte, or 4-MByte flat address space. Page-Directory-Pointer Table—An array of four 64-bit entries, each of which points to a page directory. This data structure is only used when the physical address extension is enabled (refer to Section 3.8., “Physical Address Extension”). • • These tables provide access to either 4-KByte or 4-MByte pages when normal 32-bit physical addressing is being used and to either 4-KByte, 2-MByte, or 4-MByte pages when extended (36bit) physical addressing is being used. Table 3-3 shows the page size and physical address size obtained from various settings of the paging control flags. Each page-directory entry contains a PS (page size) flag that specifies whether the entry points to a page table whose entries in turn point to 4-KByte pages (PS set to 0) or whether the page-directory entry points directly to a 4MByte or 2-MByte page (PSE or PAE set to 1 and PS set to 1). Table 3-3. Page Sizes and Physical Address Sizes PG Flag, CR0 0 1 1 1 1 1 PAE Flag, CR4 X 0 0 0 1 1 PSE Flag, CR4 X 0 1 1 X X PS Flag, PDE X X 0 1 0 1 Page Size — 4 KBytes 4 KBytes 4 MBytes 4 KBytes 2 MBytes Physical Address Size Paging Disabled 32 Bits 32 Bits 32 Bits 36 Bits 36 Bits LINEAR ADDRESS TRANSLATION (4-KBYTE PAGES) Figure 3-12 shows the page directory and page-table hierarchy when mapping linear addresses to 4-KByte pages. The entries in the page directory point to page tables, and the entries in a page table point to pages in physical memory. This paging method can be used to address up to 220 pages, which spans a linear address space of 232 bytes (4 GBytes). 3-20 PROTECTED-MODE...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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