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The address space of the p6 family pentium and

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Unformatted text preview: above the stack limit, in which case a stack fault exception (#SS) will be generated. On the Intel486™ processor, stack location at ESP plus 2 may be less than the stack limit and no exception is generated. For a POP-to-memory instruction that meets the following conditions: • • • The stack segment size is 16-bit Any 32-bit addressing form with the SIB byte specifying ESP as the base register The initial stack pointer is FFFCh (32-bit operand) or FFFEh (16-bit operand) and will wrap around to 0h as a result of the POP operation the result of the memory write is specific to the processor-family. For example, in Pentium® II and Pentium® Pro processors, the result of the memory write is SS:0h plus any scaled index and displacement. In Pentium® and Pentium® Pro processors, the result of the memory write may be either a stack fault (real mode or protected mode with stack segment size of 64Kbyte), or write to SS:10000h plus any scaled index and displacement (protected mode and stack segment size exceeds 64Kbyte). 18.24.2. Error Code Pushes The Intel486™ processor implements the error code pushed on the stack as a 16-bit value. When pushed onto a 32-bit stack, the Intel486™ processor only pushes 2 bytes and updates ESP by 4. The P6 family and Pentium® processors’ error code is a full 32 bits with the upper 16 bits set to zero. The P6 family and Pentium® processors, therefore, push 4 bytes and update ESP by 4. Any code that relies on the state of the upper 16 bits may produce inconsistent results. 18.24.3. Fault Handling Effects on the Stack During the handling of certain instructions, such as CALL and PUSHA, faults may occur in different sequences for the different processors. For example, during far calls, the Intel486™ processor pushes the old CS and EIP before a possible branch fault is resolved. A branch fault 18-33 INTEL ARCHITECTURE COMPATIBILITY is a fault from a branch instruction occurring from a segment limit or access rights violation. If a branch fault is taken, the Intel486™ and P6 family processors will have corrupted memory below the stack pointer. However, the ESP register is backed up to make the instruction restartable. The P6 family processors issue the branch before the pushes. Therefore, if a branch fault does occur, these processors do not corrupt memory below the stack pointer. This implementation difference, however, does not constitute a compatibility problem, as only values at or above the stack pointer are considered to be valid. 18.24.4. Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate If a call or interrupt is made from a 32-bit stack environment through a 16-bit gate, only 16 bits of the old ESP can be pushed onto the stack. On the subsequent RET/IRET, the 16-bit ESP is popped but the full 32-bit ESP is updated since control is being resumed in a 32-bit stack environment. The Intel486™ processor writes the SS selector into the upper 16 bits of ESP. The P6 family and Pentium® processors write zeros into the upper 16 bits. 18.25. MIXING 16- AND 32-BIT SEGMENTS The features of the 16-bit Intel 286 processor are an object-code compatible subset of those of the 32-bit Intel Architecture processors. The D (default operation size) flag in segment descriptors indicates whether the processor treats a code or data segment as a 16-bit or 32-bit segment; the B(default stack size) flag in segment descriptors indicates whether the processor treats a stack segment as a 16-bit or 32-bit segment. The segment descriptors used by the Intel 286 processor are supported by the 32-bit Intel Architecture processors if the Intel-reserved word (highest word) of the descriptor is clear. On the 32-bit Intel Architecture processors, this word includes the upper bits of the base address and the segment limit. The segment descriptors for data segments, code segments, local descriptor tables (there are no descriptors for global descriptor tables), and task gates are the same for the 16- and 32-bit processors. Other 16-bit descriptors (TSS segment, call gate, interrupt gate, and trap gate) are supported by the 32-bit processors. The 32-bit processors also have descriptors for TSS segments, call gates, interrupt gates, and trap gates that support the 32-bit architecture. Both kinds of descriptors can be used in the same system. For those segment descriptors common to both 16- and 32-bit processors, clear bits in the reserved word cause the 32-bit processors to interpret these descriptors exactly as an Intel 286 processor does, that is: • • • Base Address—The upper 8 bits of the 32-bit base address are clear, which limits base addresses to 24 bits. Limit—The upper 4 bits of the limit field are clear, restricting the value of the limit field to 64 Kbytes. Granularity bit—The G (granularity) flag is clear, indicating the value of the 16-bit limit is interpreted in units of 1 byte. 18-34 INTEL ARCHITECTURE COMPATIBILITY • • Big bit—In a data-segment descriptor, the B flag is clear in the segment descr...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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