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Unformatted text preview: APIC agent's (the BSPs) arbitration priority to 0. The FIPI is therefore issued by a priority 0 agent and has to wait until all other agents have issued their BIPI's. When the BSP receives the FIPI that it issued (t=5), it will start fetching code at the reset vector (Intel Architecture address).
System (CPU) Bus P6 Family Processor A P6 Family Processor B P6 Family Processor C P6 Family Processor D APIC Bus t=0 t=1 t=2 t=3 t=4 t=5 BIPI.A BIPI.B BIPI.C Serial Bus Activity BIPI.D FIPI Figure 7-19. SMP System 5. All application processors (non-BSP processors) remain in a “halted” state and can only be woken up by SIPIs issued by another processor (note an AP in the startup IPI loop will also respond to BINIT and snoops). 7-49 8
Processor Management and Initialization PROCESSOR MANAGEMENT AND INITIALIZATION CHAPTER 8 PROCESSOR MANAGEMENT AND INITIALIZATION
This chapter describes the facilities provided for managing processor wide functions and for initializing the processor. The subjects covered include: processor initialization, FPU initialization, processor configuration, feature determination, mode switching, the MSRs (in the Pentium® and P6 family processors), and the MTRRs (in the P6 family processors). 8.1. INITIALIZATION OVERVIEW Following power-up or an assertion of the RESET# pin, each processor on the system bus performs a hardware initialization of the processor (known as a hardware reset) and an optional built-in self-test (BIST). A hardware reset sets each processor’s registers to a known state and places the processor in real-address mode. It also invalidates the internal caches, translation lookaside buffers (TLBs) and the branch target buffer (BTB). At this point, the action taken depends on the processor family: • P6 family processors—All the processors on the system bus (including a single processor in a uniprocessor system) execute the multiple processor (MP) initialization protocol across the APIC bus. The processor that is selected through this protocol as the bootstrap processor (BSP) then immediately starts executing software-initialization code in the current code segment beginning at the offset in the EIP register. The application (non-BSP) processors (AP) go into a halt state while the BSP is executing initialization code. Refer to Section 7.7., “Multiple-Processor (MP) Initialization Protocol” in Chapter 7, MultipleProcessor Management for more details. Note that in a uniprocessor system, the single P6 family processor automatically becomes the BSP. Pentium® processors—In either a single- or dual- processor system, a single Pentium® processor is always pre-designated as the primary processor. Following a reset, the primary processor behaves as follows in both single- and dual-processor systems. Using the dualprocessor (DP) ready initialization protocol, the primary processor immediately starts executing software-initialization code in the current code segment beginning at the offset in the EIP register. The secondary processor (if there is one) goes into a halt state. (Refer to Section 7.6., “Dual-Processor (DP) Initialization Protocol” in Chapter 7, MultipleProcessor Management for more details.) Intel486™ processor—The primary processor (or single processor in a uniprocessor system) immediately starts executing software-initialization code in the current code segment beginning at the offset in the EIP register. (The Intel486™ does not automatically execute a DP or MP initialization protocol to determine which processor is the primary processor.) • • The software-initialization code performs all system-specific initialization of the BSP or primary processor and the system logic.
8-1 PROCESSOR MANAGEMENT AND INITIALIZATION At this point, for MP (or DP) systems, the BSP (or primary) processor wakes up each AP (or secondary) processor to enable those processors to execute self-configuration code. When all processors are initialized, configured, and synchronized, the BSP or primary processor begins executing an initial operating-system or executive task. The floating-point unit (FPU) is also initialized to a known state during hardware reset. FPU software initialization code can then be executed to perform operations such as setting the precision of the FPU and the exception masks. No special initialization of the FPU is required to switch operating modes. Asserting the INIT# pin on the processor invokes a similar response to a hardware reset. The major difference is that during an INIT, the internal caches, MSRs, MTRRs, and FPU state are left unchanged (although, the TLBs and BTB are invalidated as with a hardware reset). An INIT provides a method for switching from protected to real-address mode while maintaining the contents of the internal caches. 8.1.1. Processor State After Reset Table 8-1 shows the state of the flags and other registers following power-up for the Pentium® Pro, Pentium®, and Intel486™ processors. The state of control register CR0 is 60000010H (refer to Figure 8-1), which places the processor is in real-address mode with paging disabled. 8.1.2. Processor Built-In Self-Test (BIST) Hardware may request that the BIST be performed at power-up. The EAX register is cleared (0H) if the processor passes the BIST. A...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10