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Unformatted text preview: , 32-byte cache line size. - Intel486™ processor: System specific. - P6 family processors: 32 entries, 4-way set associative. - Pentium® processor: 32 entries, 4-way set associative; fully set associative for Pentium® processors with MMX™ technology. - Intel486™ processor: 32 entries, 4-way set associative, instruction and data TLB combined. - Pentium® and P6 family processors: 64 entries, 4-way set associative; fully set associative for Pentium® processors with MMX™ technology. - Intel486™ processor: (see Instruction TLB). - P6 family processors: 2 entries, fully associative - Pentium® processor: Uses same TLB as used for 4-KByte pages. - Intel486™ processor: None (large pages not supported). - P6 family processors: 8 entries, 4-way set associative. - Pentium® processor: 8 entries, 4-way set associative; uses same TLB as used for 4-KByte pages in Pentium® processors with MMX™ technology. - Intel486™ processor: None (large pages not supported). - P6 family processors: 12 entries. - Pentium® processor: 2 buffers, 1 entry each (Pentium® processors with MMX™ technology have 4 buffers for 4 entries). - Intel486™ processor: 4 entries. L1 Data Cache1 L2 Unified Cache2,3 Instruction TLB (4KByte Pages)1 Data TLB (4-KByte Pages)1 Instruction TLB (Large Pages) Data TLB (Large Pages) Write Buffer NOTES: 1. In the Intel486™ processor, the L1 cache is a unified instruction and data cache, and the TLB is a unified instruction and data TLB. 2. In the Intel486™ and Pentium® processors, the L2 cache is external to the processor package and optional. 3. In the Pentium® Pro, Pentium® II, and Pentium® III processors, the L2 cache is internal to the processor package. 9-3 MEMORY CACHE CONTROL The L2 cache is a unified cache for storage of both instructions and data. It is closely coupled to the L1 cache through the processor’s cache bus (for the P6 family processors) or the system bus (for the Pentium® and Intel486™ processors). The cache lines for the P6 family and Pentium® processors’ L1 and L2 caches are 32 bytes wide. The processor always reads a cache line from system memory beginning on a 32-byte boundary. (A 32-byte aligned cache line begins at an address with its 5 least-significant bits clear.) A cache line can be filled from memory with a 4-transfer burst transaction. The caches do not support partially-filled cache lines, so caching even a single doubleword requires caching an entire line. (The cache line size for the Intel486™ processor is 16 bytes.) The L1 and L2 caches are available in all execution modes. Using these caches greatly improves the performance of the processor both in single- and multiple-processor systems. Caching can also be used in system management mode (SMM); however, it must be handled carefully. For more information, see Section 12.4.2., “SMRAM Caching”, in Chapter 12, System Management Mode (SMM). The TLBs store the most recently used page-directory and page-table entries. They speed up memory accesses when paging is enabled by reducing the number of memory accesses that are required to read the page tables stored in system memory. The TLBs are divided into four groups: instruction TLBs for 4-KByte pages, data TLBs for 4-KByte pages; instruction TLBs for large pages (2-MByte or 4-MByte pages), and data TLBs for large pages. (Only 4-KByte pages are supported for Intel386™ and Intel486™ processors.) The TLBs are normally active only in protected mode with paging enabled. When paging is disabled or the processor is in realaddress mode, the TLBs maintain their contents until explicitly or implicitly flushed. For more information, see Section 9.10., “Invalidating the Translation Lookaside Buffers (TLBs)”. The write buffer is associated with the processors instruction execution units. It allows writes to system memory and/or the internal caches to be saved and in some cases combined to optimize the processor’s bus accesses. The write buffer is always enabled in all execution modes. The processor’s caches are for the most part transparent to software. When enabled, instructions and data flow through these caches without the need for explicit software control. However, knowledge of the behavior of these caches may be useful in optimizing software performance. For example, knowledge of cache dimensions and replacement algorithms gives an indication of how large of a data structure can be operated on at once without causing cache thrashing. In multiprocessor systems, maintenance of cache consistency may, in rare circumstances, require intervention by system software. For these rare cases, the processor provides privileged cache control instructions for use in flushing caches. 9.2. CACHING TERMINOLOGY The Intel Architecture (beginning with the Pentium® processor) uses the MESI (modified, exclusive, shared, invalid) cache protocol to maintain consistency with internal caches and caches in other processors. For more information, see Section 9.4., “Cache Control Protocol”. (The Intel486™ processor uses an implementation defined caching protocol that operates in a similar manner to the MESI protocol.) 9-4 MEMORY CACHE CONTROL When the processor recognizes that an operand being read from memory is cacheable, the processor reads an entire cache line into the appropriate cache (L1, L2...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10