This preview shows page 1. Sign up to view the full content.
Unformatted text preview: flag in the control register CR0 image stored in the new task’s TSS. 12. Loads the task register with the segment selector and descriptor for the new task's TSS. 6-12 TASK MANAGEMENT 13. Loads the new task’s state from its TSS into processor. Any errors associated with the loading and qualification of segment descriptors in this step occur in the context of the new task. The task state information that is loaded here includes the LDTR register, the PDBR (control register CR3), the EFLAGS register, the EIP register, the general-purpose registers, and the segment descriptor parts of the segment registers. 14. Begins executing the new task. (To an exception handler, the first instruction of the new task appears not to have been executed.) The state of the currently executing task is always saved when a successful task switch occurs. If the task is resumed, execution starts with the instruction pointed to by the saved EIP value, and the registers are restored to the values they held when the task was suspended. When switching tasks, the privilege level of the new task does not inherit its privilege level from the suspended task. The new task begins executing at the privilege level specified in the CPL field of the CS register, which is loaded from the TSS. Because tasks are isolated by their separate address spaces and TSSs and because privilege rules control access to a TSS, software does not need to perform explicit privilege checks on a task switch. Table 6-1 shows the exception conditions that the processor checks for when switching tasks. It also shows the exception that is generated for each check if an error is detected and the segment that the error code references. (The order of the checks in the table is the order used in the P6 family processors. The exact order is model specific and may be different for other Intel Architecture processors.) Exception handlers designed to handle these exceptions may be subject to recursive calls if they attempt to reload the segment selector that generated the exception. The cause of the exception (or the first of multiple causes) should be fixed before reloading the selector.
Table 6-1. Exception Conditions Checked During a Task Switch
Condition Checked Segment selector for a TSS descriptor references the GDT and is within the limits of the table. TSS descriptor is present in memory. TSS descriptor is not busy (for task switch initiated by a call, interrupt, or exception). TSS descriptor is not busy (for task switch initiated by an IRET instruction). TSS segment limit greater than or equal to 108 (for 32bit TSS) or 44 (for 16-bit TSS). Registers are loaded from the values in the TSS. LDT segment selector of new task is valid 3. Code segment DPL matches segment selector RPL. SS segment selector is valid . Stack segment is present in memory.
2 Exception1 #GP #NP #GP (for JMP, CALL, INT) #TS (for IRET) #TS Error Code Reference2 New Task’s TSS New Task’s TSS Task’s back-link TSS New Task’s TSS New Task’s TSS #TS #TS #TS #SF New Task’s LDT New Code Segment New Stack Segment New Stack Segment 6-13 TASK MANAGEMENT Table 6-1. Exception Conditions Checked During a Task Switch (Contd.)
Stack segment DPL matches CPL. LDT of new task is present in memory. CS segment selector is valid . Code segment is present in memory. Stack segment DPL matches selector RPL. DS, ES, FS, and GS segment selectors are valid . DS, ES, FS, and GS segments are readable. DS, ES, FS, and GS segments are present in memory. DS, ES, FS, and GS segment DPL greater than or equal to CPL (unless these are conforming segments). NOTES: 1. #NP is segment-not-present exception, #GP is general-protection exception, #TS is invalid-TSS exception, and #SF is stack-fault exception. 2. The error code contains an index to the segment descriptor referenced in this column. 3. A segment selector is valid if it is in a compatible type of table (GDT or LDT), occupies an address within the table’s segment limit, and refers to a compatible type of descriptor (for example, a segment selector in the CS register only is valid when it points to a code-segment descriptor).
3 3 #TS #TS #TS #NP #TS #TS #TS #NP #TS New stack segment New Task’s LDT New Code Segment New Code Segment New Stack Segment New Data Segment New Data Segment New Data Segment New Data Segment The TS (task switched) flag in the control register CR0 is set every time a task switch occurs. System software uses the TS flag to coordinate the actions of floating-point unit when generating floating-point exceptions with the rest of the processor. The TS flag indicates that the context of the floating-point unit may be different from that of the current task. Refer to Section 2.5., “Control Registers” in Chapter 2, System Architecture Overview for a detailed description of the function and use of the TS flag. 6.4. TASK LINKING The previous task link field of the TSS (sometimes called the “backlink”) and the NT flag in the EFLAGS register are used to return execution to the previous task. The NT flag indicates whether the currently executing task is nested...
View Full Document
- Spring '10