IntelSoftwareDevelopersManual

The flag ze for the divide by zero exception is bit 2

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Unformatted text preview: of operands. If the invalid operation exception is masked, the processor sets the IE flag in MXCSR and returns the single-precision QNaN indefinite value or another QNaN value (derived from a NaN input operand) to the destination operand. This value overwrites the destination register specified by the instruction. If the invalid operation exception is not masked, the processor sets the IE flag in MXCSR and an exception handler is invoked (see Section 11.7.2.3., “Software Exception Handling Unmasked Exceptions”) and the operands remain unchanged. The processor can detect a variety of invalid arithmetic operations that can be coded in a program. These operations generally indicate a programming error, such as dividing ∞ by ∞. Table 11-8 lists the SIMD floating-point invalid arithmetic operations that the processor detects. This group includes the invalid operations defined in IEEE Std. 854. The flag (IE) for this exception is bit 0 of MXCSR, and the mask bit (IM) is bit 7 of MXCSR. The invalid operation exception is not affected by the flush-to-zero mode. 11-17 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING Table 11-8. Invalid Arithmetic Operations and the Masked Responses to Them Condition ADDPS/ADDSS/DIVPS/DIVSS/ MULPS/MULSS/SUBPS/SUBSS with a SNaN operand. CMPPS/CMPSS with QNaN/SNaN operands (QNaN applies only for predicates "lt", "le", "nlt", "nle") COMISS with QNaN/SNaN operand(s). UCOMISS with SNaN operand(s). SQRTPS/SQRTSS with SNaN operand(s). Addition of opposite signed infinities or subtraction of like-signed infinities. Multiplication of infinity by zero. Divide of (0/0) or( Masked Response Return the Signaling NaN converted to a quiet NaN; Refer to Table 7-18, in Chapter 7, Floating-Point Unit, for more details; set #IA flag. Return a mask of all 0’s for predicates "eq", "lt", "le", and "ord", and a mask of all 1’s for predicates "neq", "nlt", "nle", and "unord"; set #IA flag. Set EFLAGS values to ’not comparable’; set #IA flag. Set EFLAGS values to ’not comparable’; set #IA flag. Return the SNan converted to a QNaN; set #IA flag; Return the QNaN Indefinite; set #IA flag. Return the QNaN Indefinite; set #IA flag. Return the QNaN Indefinite; set #IA flag. Return the QNaN Indefinite; set #IA flag. Return the Integer Indefinite; set #IA flag. ∞ / ∞ .) SQRTPS/SQRTSS of negative operands (except negative zero). Conversion to integer when the source register is a NaN, Infinity or exceeds the representable range. NOTE: RCPPS/RCPSS/RSQRTPS/RSQRTSS with QNaN/SNaN operand(s) do not raise an invalid exception. They return either the SNaN operand converted to QNaN, or the original QNaN operand. RSQRTPS/RSQRTSS with negative operands (but not for negative zero) do not raise an invalid exception, and return QNaN Indefinite. 11.7.3.2. DIVISION-BY-ZERO EXCEPTION (#Z) The processor reports a divide-by-zero exception whenever an instruction attempts to divide a finite non-zero operand by 0. This is possible with DIVPS, DIVSS. The masked response for DIVPS, DIVSS is to set the ZE flag in MXCSR and return an infinity signed with the exclusive OR of the signs of the operands. If the divide-by-zero exception is not masked, the ZE flag is set, a software exception handler is invoked (see Section 11.7.2.3., “Software Exception Handling - Unmasked Exceptions”) and the source operands remain unchanged. Note that the response for RCPPS, RSQRTPS, RCPSS and RSQRTSS is to return an infinity of the same sign as the operand. These instructions do not set any exception flags and thus are not affected by the exception masks. The flag (ZE) for the divide-by-zero exception is bit 2 of MXCSR, and the mask bit (ZM) is bit 9 of MXCSR. The divide-by-zero exception is not affected by the flush-to-zero mode. 11-18 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING 11.7.3.3. DENORMAL OPERAND EXCEPTION (#D) The processor signals the denormal operand exception if an arithmetic instruction attempts to operate on a denormal operand. When a denormal operand exception occurs and the exception is masked, the processor sets the DE flag in MXCSR, then proceeds with the instruction. Operating on denormal numbers will produce results at least as good as, and often better than, what can be obtained when denormal numbers are flushed to zero. Programmers can mask this exception so that a computation may proceed, then analyze any loss of accuracy when the final result is delivered. When a denormal operand exception occurs and the exception is not masked, the processor sets the DE bit in MXCSR and a software exception handler is invoked (see Section 11.7.2.3., “Software Exception Handling - Unmasked Exceptions”). The source operands remain unchanged. When denormal operands have reduced significance due to loss of low-order bits, it may be advisable to not operate on them. Precluding denormal operands from computations can be accompl...
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