IntelSoftwareDevelopersManual

The impact of this difference on exiting software is

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Unformatted text preview: vector 6). Undefined floating-point opcodes, like legal floating-point opcodes, cause a device not available exception (#NM, interrupt vector 7) when either the TS or EM flag in control register CR0 is set. The P6 family, Pentium®, and Intel486™ processors do not check for floating-point error conditions on encountering an undefined floating-point opcode. 18.12.6.7. ASSERTION OF THE FERR# PIN When using the MS-DOS compatibility mode for handing floating-point exceptions, the FERR# pin must be connected to an input to an external interrupt controller. An external interrupt is then generated when the FERR# output drives the input to the interrupt controller and the interrupt controller in turn drives the INTR pin on the processor. For the P6 family and Intel386™ processors, an unmasked floating-point exception always causes the FERR# pin to be asserted upon completion of the instruction that caused the exception. For the Pentium® and Intel486™ processors, an unmasked floating-point exception may cause the FERR# pin to be asserted either at the end of the instruction causing the exception or immediately before execution of the next floating-point instruction. (Note that the next floating-point instruction would not be executed until the pending unmasked exception has been handled.) Refer to Appendix D in the Intel Architecture Software Developer’s Manual, Volume 1, for a complete description of the required mechanism for handling floating-point exceptions using the MS-DOS compatibility mode. 18.12.6.8. INVALID OPERATION EXCEPTION ON DENORMALS An invalid operation exception is not generated on the 32-bit Intel Architecture FPUs upon encountering a denormal value when executing a FSQRT, FDIV, or FPREM instruction or upon conversion to BCD or to integer. The operation proceeds by first normalizing the value. On the 16-bit Intel Architecture math coprocessors, upon encountering this situation, the invalid operation exception is generated. This difference has no impact on existing software. Software running on the 32-bit Intel Architecture FPUs continues to execute in cases where the 16-bit Intel Architecture math coprocessors trap. The reason for this change was to eliminate an exception from being raised. 18.12.6.9. ALIGNMENT CHECK EXCEPTIONS (#AC) If alignment checking is enabled, a misaligned data operand on the P6 family, Pentium®, and Intel486™ processors causes an alignment check exception (#AC) when a program or procedure is running at privilege-level 3, except for the stack portion of the FSAVE/FNSAVE/FXSAVE and FRSTOR/FXRSTOR instructions. 18-13 INTEL ARCHITECTURE COMPATIBILITY 18.12.6.10. SEGMENT NOT PRESENT EXCEPTION DURING FLDENV On the Intel486™ processor, when a segment not present exception (#NP) occurs in the middle of an FLDENV instruction, it can happen that part of the environment is loaded and part not. In such cases, the FPU control word is left with a value of 007FH. The P6 family and Pentium® processors ensure the internal state is correct at all times by attempting to read the first and last bytes of the environment before updating the internal state. 18.12.6.11. DEVICE NOT AVAILABLE EXCEPTION (#NM) The device-not-available exception (#NM, interrupt 7) will occur in the P6 family, Pentium®, and Intel486™ processors as described in Section 2.5., “Control Registers” in Chapter 2, System Architecture Overview, and Section 5.12., “Exception and Interrupt Reference” in Chapter 5, Interrupt and Exception Handling . 18.12.6.12. COPROCESSOR SEGMENT OVERRUN EXCEPTION The coprocessor segment overrun exception (interrupt 9) does not occur in the P6 family, Pentium®, and Intel486™ processors. In situations where the Intel 387 math coprocessor would cause an interrupt 9, the P6 family, Pentium®, and Intel486™ processors simply abort the instruction. To avoid undetected segment overruns, it is recommended that the floating-point save area be placed in the same page as the TSS. This placement will prevent the FPU environment from being lost if a page fault occurs during the execution of an FLDENV, FRSTOR, or FXRSTOR instructions while the operating system is performing a task switch. 18.12.6.13. GENERAL PROTECTION EXCEPTION (#GP) A general-protection exception (#GP, interrupt 13) occurs if the starting address of a floatingpoint operand falls outside a segment’s size. An exception handler should be included to report these programming errors. 18.12.6.14. FLOATING-POINT ERROR EXCEPTION (#MF) In real mode and protected mode (not including virtual-8086 mode), interrupt vector 16 must point to the floating-point exception handler. In virtual 8086 mode, the virtual-8086 monitor can be programmed to accommodate a different location of the interrupt vector for floating-point exceptions. 18.12.7. Changes to Floating-Point Instructions This section identifies the differences in floating-point instructions for the various Intel FPU and math coprocessor architectures, the reason for the differences, and their impact on s...
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