Unformatted text preview: e local APIC incorporates an error status register to log and report errors to the processor. In the P6 family processors, the local APIC incorporates an additional local vector table entry to handle performance monitoring counter interrupts. 7.6. DUAL-PROCESSOR (DP) INITIALIZATION PROTOCOL The Pentium® processor contains an internal dual-processing (DP) mechanism that permits two processors to be initialized and configured for tightly coupled symmetric multiprocessing (SMP). The DP initialization protocol supports the controlled booting and configuration of the two Pentium® processors. When configuration has been completed, the two Pentium® processors can share the processing load for the system and share the handling of interrupts received from the system’s I/O APIC. The Pentium® DP initialization protocol defines two processors: • • Primary processor (also called the bootstrap processor, BSP)—This processor boots itself, configures the APIC environment, and starts the second processor. Secondary processor (also called the dual processor, DP)—This processor boots itself then waits for a startup signal from the primary processor. Upon receiving the startup signal, it completes its configuration. Appendix C, Dual-Processor (DP) Bootup Sequence Example (Specific to Pentium® Processors) gives an example (with code) of the bootup sequence for two Pentium® processors operating in a DP configuration. 7-45 MULTIPLE-PROCESSOR MANAGEMENT Appendix E, Programming the LINT0 and LINT1 Inputs describes (with code) how to program the LINT[0:1] pins of the processor’s local APICs after a dual-processor configuration has been completed. 7.7. MULTIPLE-PROCESSOR (MP) INITIALIZATION PROTOCOL The Intel Architecture (beginning with the Pentium® Pro processors) defines a multipleprocessor (MP) initialization protocol, for use with both single- and multiple-processor systems. (Here, multiple processors is defined as two or more processors.) The primary goals of this protocol are as follows: • To permit sequential or controlled booting of multiple processors (from 2 to 4) with no dedicated system hardware. The initialization algorithm is not limited to 4 processors; it can support supports from 1 to 15 processors in a multiclustered system when the APIC busses are tied together. Larger systems are not supported. To be able to initiate the MP protocol without the need for a dedicated signal or BSP. To provide fault tolerance. No single processor is geographically designated the BSP. The BSP is determined dynamically during initialization. • • The following sections describe an MP initialization protocol. Appendix D, Multiple-Processor (MP) Bootup Sequence Example (Specific to P6 Family Processors) gives an example (with code) of the bootup sequence for two P6 family processors operating in an MP configuration. Appendix E, Programming the LINT0 and LINT1 Inputs describes (with code) how to program the LINT[0:1] pins of the processor’s local APICs after an MP configuration has been completed. 7.7.1. MP Initialization Protocol Requirements and Restrictions The MP protocol imposes the following requirements and restrictions on the system: • • An APIC clock (APICLK) must be provided on all systems based on the P6 family processors (excluding mobile processors and modules). All interrupt mechanisms must be disabled for the duration of the MP protocol algorithm, including the window of time between the assertion of INIT# or receipt of an INIT IPI by the application processors and the receipt of a STARTUP IPI by the application processors. That is, requests generated by interrupting devices must not be seen by the local APIC unit (on board the processor) until the completion of the algorithm. Failure to disable the interrupt mechanisms may result in processor shutdown. The MP protocol should be initiated only after a hardware reset. After completion of the protocol algorithm, a flag is set in the APIC base MSR of the BSP (APIC_BASE.BSP) to indicate that it is the BSP. This flag is cleared for all other processors. If a processor or the complete system is subject to an INIT sequence (either through the INIT# pin or an INIT • 7-46 MULTIPLE-PROCESSOR MANAGEMENT IPI), then the MP protocol is not re-executed. Instead, each processor examines its BSP flag to determine whether the processor should boot or wait for a STARTUP IPI. 7.7.2. MP Protocol Nomenclature The MP initialization protocol defines two classes of processors: • • The bootstrap processor (BSP)—This primary processor is dynamically selected by the MP initialization algorithm. After the BSP has been selected, it configures the APIC environment, and starts the secondary processors, under software control. Application processors (APs)—These secondary processors are the remainder of the processors in a MP system that were not selected as the BSP. The APs complete a minimal self-configuration, then wait for a startup signal from the BSP processor. Upon receiving a startup signal, an AP completes its configuration. Tab...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10