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Unformatted text preview: cannot be precisely represented in binary form. This exception occurs frequently and indicates that some (normally acceptable) accuracy has been lost. The exception is supported for applications that need to perform exact arithmetic only. Because the rounded result is generally satisfactory for most applications, this exception is commonly masked. If the inexact result exception is masked when an inexact result condition occurs and a numeric overflow or underflow condition has not occurred, the processor sets the inexact (#P) status flag (PE flag) and stores the rounded result in the destination operand. The current rounding mode determines the method used to round the result (refer to Section 18.104.22.168., “Rounding Control Field”). If the inexact result exception is not masked when an inexact result occurs and numeric overflow or underflow has not occurred, the operands are left unaltered, the PE flag is set in MXCSR, the inexact (#P) status flag is set, and a software exception handler is invoked (see Section 22.214.171.124., “Software Exception Handling - Unmasked Exceptions”). If an inexact result occurs in conjunction with numeric overflow or underflow, one of the following operations is carried out: • If an inexact result occurs along with masked overflow or underflow, the OE or UE flag and the PE flag are set in MXCSR and the result is stored as described for the overflow or underflow exceptions (see Section 126.96.36.199., “Numeric Overflow Exception (#O)”. or Section 188.8.131.52., “Numeric Underflow Exception (#U)”). If the inexact result exception is unmasked, the processor also invokes the software exception handler. If an inexact result occurs along with unmasked overflow or underflow, the OE or UE flag and the PE flag are set and the software exception handler is invoked. • Note that the inexact result flag is not set by RCPPS, RSQRTPS, RCPSS and RSQRTSS, since these instructions are combinatorial and are not affected by the exception masks. The inexact result exception flag (PE) is bit 5 of MXCSR, and the mask bit (PM) is bit 12 of MXCSR. 11-21 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING In flush-to-zero mode, the inexact result exception is reported along with the underflow exception (the latter must be masked). 11.7.4. Effect of Streaming SIMD Extensions Instructions on Pending Floating-Point Exceptions Unlike MMX™ instructions which will generate a floating-point error (#MF) prior to executing the MMX™ instruction, execution of a Streaming SIMD Extensions instruction does not generate a floating-point error (#MF) prior to executing the instruction. Hence they will not catch pending x87 floating-point exceptions. In addition, they will not cause assertion of FERR# (independent of the value of CR0.NE) and they ignore the assertion/de-assertion of IGNNE#. 11.8. DEBUGGING
The debug facilities of the Intel Architecture operate in the same manner when executing Streaming SIMD Extensions as when executing other Intel Architecture instructions. These facilities enable debuggers to debug code utilizing these instructions. To correctly interpret the contents of the Pentium® III processor registers from the FXSAVE image in memory, a debugger needs to take account of the relationship between the floatingpoint register’s logical locations relative to TOS and the MMX™ register’s physical locations (refer to Section 10.6., “Debugging”, Chapter 10, MMX™ Technology System Programming). In addition it needs to have knowledge of the SIMD floating-point registers and the state save data area used by the FXSAVE instruction. Comparisons of the Streaming SIMD Extensions and x87 results can be performed within the Pentium® III processor at the internal single precision format and/or externally at the memory single precision format. The internal format comparison is required to allow the partitioning of the data space to reduce test time. 11-22 12
System Management Mode SYSTEM MANAGEMENT MODE (SMM) CHAPTER 12 SYSTEM MANAGEMENT MODE (SMM)
This chapter describes the Intel Architecture’s System Management Mode (SMM) architecture. SMM was introduced into the Intel Architecture in the Intel386™ SL processor (a mobile specialized version of the Intel386™ processor). It is also available in the Intel486™ processors (beginning with the Intel486™ SL and Intel486™ enhanced versions) and in the Intel Pentium® and P6 family processors. For a detailed description of the hardware that supports SMM, refer to the developer’s manuals for each of the Intel Architecture processors. 12.1. SYSTEM MANAGEMENT MODE OVERVIEW
SMM is a special-purpose operating mode provided for handling system-wide functions like power management, system hardware control, or proprietary OEM-designed code. It is intended for use only by system firmware, not by applications software or general-purpose systems software. The main benefit of SMM is that it offers a distinct and easily isolated processor environment that operates transparently to the operating system or executive and sof...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10