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Unformatted text preview: y to software. Several mechanisms are available, however, that allow software and hardware to invalidate the TLBs either explicitly or as a side effect of another operation. The INVLPG instruction invalidates the TLB for a specific page. This instruction is the most efficient in cases where software only needs to invalidate a specific page, because it improves performance over invalidating the whole TLB. This instruction is not affected by the state of the G flag in a page-directory or page-table entry. The following operations invalidate all TLB entries except global entries. (A global entry is one for which the G (global) flag is set in its corresponding page-directory or page-table entry. The global flag was introduced into the Intel Architecture in the P6 family processors, see Section 9.5., “Cache Control”.) • • • • • • Writing to control register CR3. A task switch that changes control register CR3. The following operations invalidate all TLB entries, irrespective of the setting of the G flag: Asserting or de-asserting the FLUSH# pin. (P6 family processors only.) Writing to an MTRR (with a WRMSR instruction). Writing to control register CR0 to modify the PG or PE flag. (P6 family processors only.) Writing to control register CR4 to modify the PSE, PGE, or PAE flag. See Section 3.7., “Translation Lookaside Buffers (TLBs)”, in Chapter 3, Protected-Mode Memory Management, for additional information about the TLBs. 9.11. WRITE BUFFER
Intel Architecture processors temporarily store each write (store) to memory in a write buffer. The write buffer improves processor performance by allowing the processor to continue executing instructions without having to wait until a write to memory and/or to a cache is complete. It also allows writes to be delayed for more efficient use of memory-access bus cycles. 9-17 MEMORY CACHE CONTROL In general, the existence of the write buffer is transparent to software, even in systems that use multiple processors. The processor ensures that write operations are always carried out in program order. It also insures that the contents of the write buffer are always drained to memory in the following situations: • • • • • • When an exception or interrupt is generated. (P6 family processors only.) When a serializing instruction is executed. When an I/O instruction is executed. When a LOCK operation is performed. (P6 family processors only.) When a BINIT operation is performed. (Pentium® III processors only.) When using SFENCE to order stores. The discussion of write ordering in Section 7.2., “Memory Ordering”, in Chapter 7, MultipleProcessor Management, gives a detailed description of the operation of the write buffer. 9.12. MEMORY TYPE RANGE REGISTERS (MTRRS)
The following section pertains only to the P6 family processors. The memory type range registers (MTRRs) provide a mechanism for associating the memory types with physical-address ranges in system memory. For more information, see Section 9.3., “Methods of Caching Available”. They allow the processor to optimize operations for different types of memory such as RAM, ROM, frame-buffer memory, and memory-mapped I/O devices. They also simplify system hardware design by eliminating the memory control pins used for this function on earlier Intel Architecture processors and the external logic needed to drive them. The MTRR mechanism allows up to 96 memory ranges to be defined in physical memory, and it defines a set of model-specific registers (MSRs) for specifying the type of memory that is contained in each range. Table 9-6 shows the memory types that can be specified and their properties; Figure 9-3 shows the mapping of physical memory with MTRRs. See Section 9.3., “Methods of Caching Available”, for a more detailed description of each memory type. Following a hardware reset, a P6 family processor disables all the fixed and variable MTRRs, which in effect makes all of physical memory uncachable. Initialization software should then set the MTRRs to a specific, system-defined memory map. Typically, the BIOS (basic input/output system) software configures the MTRRs. The operating system or executive is then free to modify the memory map using the normal page-level cacheability attributes. In a multiprocessor system, different P6 family processors MUST use the identical MTRR memory map so that software has a consistent view of memory, independent of the processor executing a program. 9-18 MEMORY CACHE CONTROL Table 9-6. MTRR Memory Types and Their Properties
Encoding in MTRR 0 1 4 5 6 2, 3, 7 through 255 Cacheable in L1 and L2 Caches No No Yes Yes for reads, no for writes Yes Writeback Cacheable No No No No Yes Allows Speculative Reads No Yes Yes Yes Yes Memory Ordering Model Strong Ordering Weak Ordering Speculative Processor Ordering Speculative Processor Ordering Speculative Processor Ordering Mnemonic Uncacheable (UC) Write Combining (WC) Write-through (WT) Write-protected (WP) Writeback (WB) Reserved Encoding...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10