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Unformatted text preview: DR6 on the P6 family and Pentium® processors; however, it is possible to write a 1 in this bit on the Intel486™ processor. Refer to Table 8-1 in Chapter 8, Processor Management and Initialization for the different setting of this register following a power-up or hardware reset. 18.17.2. Differences in Debug Register DR7
The P6 family and Pentium® processors determines the type of breakpoint access by the R/W0 through R/W3 fields in debug control register DR7 as follows: 00 01 10 11 Break on instruction execution only. Break on data writes only. Undefined if the DE flag in control register CR4 is cleared; break on I/O reads or writes but not instruction fetches if the DE flag in control register CR4 is set. Break on data reads or writes but not instruction fetches. 18-24 INTEL ARCHITECTURE COMPATIBILITY On the P6 family and Pentium® processors, reserved bits 11, 12, 14 and 15 are hard-wired to 0. On the Intel486™ processor, however, bit 12 can be set. Refer to Table 8-1 in Chapter 8, Processor Management and Initialization for the different settings of this register following a power-up or hardware reset. 18.17.3. Debug Registers DR4 and DR5
Although the DR4 and DR5 registers are documented as reserved, previous generations of processors aliased references to these registers to debug registers DR6 and DR7, respectively. When debug extensions are not enabled (the DE flag in control register CR4 is cleared), the P6 family and Pentium® processors remain compatible with existing software by allowing these aliased references. When debug extensions are enabled (the DE flag is set), attempts to reference registers DR4 or DR5 will result in an invalid-opcode exception (#UD). 18.17.4. Recognition of Breakpoints
For the Pentium® processor, it is recommended that debuggers execute the LGDT instruction before returning to the program being debugged to ensure that breakpoints are detected. This operation does not need to be performed on the P6 family, Intel486™, or Intel386™ processors. 18.18. TEST REGISTERS
The implementation of test registers on the Intel486™ processor used for testing the cache and TLB has been redesigned using MSRs on the P6 family and Pentium® processors. (Note that MSRs used for this function are different on the P6 family and Pentium® processors.) The MOV to and from test register instructions generate invalid-opcode exceptions (#UD) on the P6 family processors. 18.19. Exceptions and/or Exception Conditions
This section describes the new exceptions and exception conditions added to the 32-bit Intel Architecture processors and implementation differences in existing exception handling. Refer to Chapter 5, Interrupt and Exception Handling for a detailed description of the Intel Architecture exceptions. The Pentium® III processor introduced new state with the SIMD floating-point registers. Computations involving data in these registers can produce exceptions. A new control/status register is used to determine which exception or exceptions have occurred. When an exception associated with the SIMD floating-point registers occurs, an interrupt is generated. • Streaming SIMD Extensions exception (#XF, interrupt 19)—New exceptions associated with the SIMD floating-point registers and resulting computations. 18-25 INTEL ARCHITECTURE COMPATIBILITY No new exceptions were added to the Pentium® II and Pentium® Pro processors. The set of available exceptions is the same as for the Pentium® processor. However, the following exception condition was added to the Intel Architecture with the Pentium® Pro processor: • Machine-check exception (#MC, interrupt 18)—New exception conditions. Many exception conditions have been added to the machine-check exception and a new architecture has been added for handling and reporting on hardware errors. Refer to Chapter 13, Machine-Check Architecture for a detailed description of the new conditions. The following exceptions and/or exception conditions were added to the Intel Architecture with the Pentium® processor: • Machine-check exception (#MC, interrupt 18)—New exception. This exception reports parity and other hardware errors. It is a model-specific exception and may not be implemented or implemented differently in future processors. The MCE flag in control register CR4 enables the machine-check exception. When this bit is clear (which it is at reset), the processor inhibits generation of the machine-check exception. General-protection exception (#GP, interrupt 13)—New exception condition added. An attempt to write a 1 to a reserved bit position of a special register causes a generalprotection exception to be generated. Page-fault exception (#PF, interrupt 14)—New exception condition added. When a 1 is detected in any of the reserved bit positions of a page-table entry, page-directory entry, or page-directory pointer during address translation, a page-fault exception is generated. • • The following exception was added to the Intel486™ processor...
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- Spring '10