The priorities of the flush pin and the smi are such

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Unformatted text preview: SMBASE + 8000H + 7E00H]. Table 12-1 shows the state save map. The offset in column 1 is relative to the SMBASE value plus 8000H. Reserved spaces should not be used by software. Some of the registers in the SMRAM state save area (marked YES in column 3) may be read and changed by the SMI handler, with the changed values restored to the processor registers by the RSM instruction. Some register images are read-only, and must not be modified (modifying these registers will result in unpredictable behavior). An SMI handler should not rely on any values stored in an area that is marked as reserved. Table 12-1. SMRAM State Save Map Offset (Added to SMBASE + 8000H) 7FFCH 7FF8H 7FF4H 7FF0H 7FECH 7FE8H 7FE4H 7FE0H 7FDCH 7FD8H 7FD4H Register CR0 CR3 EFLAGS EIP EDI ESI EBP ESP EBX EDX ECX Writable? No No Yes Yes Yes Yes Yes Yes Yes Yes Yes 12-5 SYSTEM MANAGEMENT MODE (SMM) Table 12-1. SMRAM State Save Map (Contd.) Offset (Added to SMBASE + 8000H) 7FD0H 7FCCH 7FC8H 7FC4H 7FC0H 7FBCH 7FB8H 7FB4H 7FB0H 7FACH 7FA8H 7FA7H - 7F04H 7F02H 7F00H 7EFCH 7EF8H 7EF7H - 7E00H NOTE: * Upper two bytes are reserved. Register EAX DR6 DR7 TR* LDT Base* GS* FS* DS* SS* CS* ES* Reserved Auto HALT Restart Field (Word) I/O Instruction Restart Field (Word) SMM Revision Identifier Field (Doubleword) SMBASE Field (Doubleword) Reserved Writable? Yes No No No No No No No No No No No Yes Yes No Yes No The following registers are saved (but not readable) and restored upon exiting SMM: • • Control register CR4 (CR4 is set to “0” while in the SMM handler). The hidden segment descriptor information stored in segment registers CS, DS, ES, FS, GS, and SS. If an SMI request is issued for the purpose of powering down the processor, the values of all reserved locations in the SMM state save must be saved to nonvolatile memory. The following state is not automatically saved and restored following an SMI and the RSM instruction, respectively: • • • • • 12-6 Debug registers DR0 through DR3. The FPU registers. The MTRRs. Control register CR2. The model-specific registers (for the P6 family and Pentium® processors) or test registers TR3 through TR7 (for the Pentium® and Intel486™ processors). SYSTEM MANAGEMENT MODE (SMM) • • • • The state of the trap controller. The machine-check architecture registers. The APIC internal interrupt state (ISR, IRR, etc.). The microcode update state. If an SMI is used to power down the processor, a power-on reset will be required before returning to SMM, which will reset much of this state back to its default values. So an SMI handler that is going to trigger power down should first read these registers listed above directly, and save them (along with the rest of RAM) to nonvolatile storage. After the power-on reset, the continuation of the SMI handler should restore these values, along with the rest of the system’s state. Anytime the SMI handler changes these registers in the processor, it must also save and restore them. NOTE A small subset of the MSRs (such as, the time-stamp counter and performance-monitoring counter) are not arbitrarily writable and therefore cannot be saved and restored. SMM-based power-down and restoration should only be performed with operating systems that do not use or rely on the values of these registers. Operating system developers should be aware of this fact and ensure that their operating-system assisted power-down and restoration software is immune to unexpected changes in these register values. 12.4.2. SMRAM Caching An Intel Architecture processor supporting SMM does not unconditionally write back and invalidate its cache before entering SMM. Therefore, if SMRAM is in a location that is “shadowed” by any existing system memory that is visible to the application or operating system, then it is necessary for the system to flush the cache upon entering SMM. This may be accomplished by asserting the FLUSH# pin at the same time as the request to enter SMM. The priorities of the FLUSH# pin and the SMI# are such that the FLUSH# will be serviced first. To guarantee this behavior, the processor requires that the following constraints on the interaction of SMI# and FLUSH# be met. In a system where the FLUSH# pin and SMI# pins are synchronous and the set up and hold times are met, then the FLUSH# and SMI# pins may be asserted in the same clock. In asynchronous systems, the FLUSH# pin must be asserted at least one clock before the SMI# pin to guarantee that the FLUSH# pin is serviced first. Note that in Pentium® processor systems that use the FLUSH# pin to write back and invalidate cache contents before entering SMM, the processor will prefetch at least one cache line in between when the Flush Acknowledge cycle is run, and the subsequent recognition of SMI# and the assertion of SMIACT#. It is the obligation of the system to ensure that these lines are not cached by returning KEN# inactive to the Pentium® processor. 12-7 SYSTEM MANAGEMENT MODE (SMM) Intel Architecture processors do not write back or invalidate their internal caches upon leavin...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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