IntelSoftwareDevelopersManual

The processor generates a debug exception for any of

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Unformatted text preview: instruction that accesses a debug register. When such a condition is detected, the BD flag in debug status register DR6 is set prior to generating the exception. This condition is provided to support incircuit emulators. (When the emulator needs to access the debug registers, emulator software can set the GD flag to prevent interference from the program 15-5 DEBUGGING AND PERFORMANCE MONITORING currently executing on the processor.) The processor clears the GD flag upon entering to the debug exception handler, to allow the handler access to the debug registers. R/W0 through R/W3 (read/write) fields (bits 16, 17, 20, 21, 24, 25, 28, and 29) Specifies the breakpoint condition for the corresponding breakpoint. The DE (debug extensions) flag in control register CR4 determines how the bits in the R/Wn fields are interpreted. When the DE flag is set, the processor interprets these bits as follows: 00—Break on instruction execution only. 01—Break on data writes only. 10—Break on I/O reads or writes. 11—Break on data reads or writes but not instruction fetches. When the DE flag is clear, the processor interprets the R/Wn bits the same as for the Intel386™ and Intel486™ processors, which is as follows: 00—Break on instruction execution only. 01—Break on data writes only. 10—Undefined. 11—Break on data reads or writes but not instruction fetches. LEN0 through LEN3 (Length) fields (bits 18, 19, 22, 23, 26, 27, 30, and 31) Specify the size of the memory location at the address specified in the corresponding breakpoint address register (DR0 through DR3). These fields are interpreted as follows: 00—1-byte length 01—2-byte length 10—Undefined 11—4-byte length If the corresponding RWn field in register DR7 is 00 (instruction execution), then the LENn field should also be 00. The effect of using any other length is undefined. Refer to Section 15.2.5., “Breakpoint Field Recognition” for further information on the use of these fields. 15.2.5. Breakpoint Field Recognition The breakpoint address registers (debug registers DR0 through DR3) and the LENn fields for each breakpoint define a range of sequential byte addresses for a data or I/O breakpoint. The LENn fields permit specification of a 1-, 2-, or 4-byte range beginning at the linear address specified in the corresponding debug register (DRn). Two-byte ranges must be aligned on word boundaries and 4-byte ranges must be aligned on doubleword boundaries. I/O breakpoint addresses are zero extended from 16 to 32 bits for purposes of comparison with the breakpoint address in the selected debug register. These requirements are enforced by the processor; it uses the LENn field bits to mask the lower address bits in the debug registers. Unaligned data or I/O breakpoint addresses do not yield the expected results. 15-6 DEBUGGING AND PERFORMANCE MONITORING A data breakpoint for reading or writing data is triggered if any of the bytes participating in an access is within the range defined by a breakpoint address register and its LENn field. Table 15-1 gives an example setup of the debug registers and the data accesses that would subsequently trap or not trap on the breakpoints. Table 15-1. Breakpointing Examples Debug Register Setup Debug Register DR0 DR1 DR2 DR3 R/Wn R/W0 = 11 (Read/Write) R/W1 = 01 (Write) R/W2 = 11 (Read/Write) R/W3 = 01 (Write) Breakpoint Address A0001H A0002H B0002H C0000H LENn LEN0 = 00 (1 byte) LEN1 = 00 (1 byte) LEN2 = 01) (2 bytes) LEN3 = 11 (4 bytes) Data Accesses Operation Data operations that trap - Read or write - Read or write - Write - Write - Read or write - Read or write - Read or write - Write - Write - Write Data operations that do not trap - Read or write - Read - Read or write - Read or write - Read - Read or write Address A0001H A0001H A0002H A0002H B0001H B0002H B0002H C0000H C0001H C0003H A0000H A0002H A0003H B0000H C0000H C0004H Access Length (In Bytes) 1 2 1 2 4 1 2 4 2 1 1 1 4 2 2 4 A data breakpoint for an unaligned operand can be constructed using two breakpoints, where each breakpoint is byte-aligned, and the two breakpoints together cover the operand. These breakpoints generate exceptions only for the operand, not for any neighboring bytes. Instruction breakpoint addresses must have a length specification of 1 byte (the LENn field is set to 00). The behavior of code breakpoints for other operand sizes is undefined. The processor recognizes an instruction breakpoint address only when it points to the first byte of an instruction. If the instruction has any prefixes, the breakpoint address must point to the first prefix. 15.3. DEBUG EXCEPTIONS The Intel Architecture processors dedicate two interrupt vectors to handling debug exceptions: vector 1 (debug exception, #DB) and vector 3 (breakpoint exception, #BP). The following 15-7 DEBUGGING AND PERFORMANCE MONITORING sections describe how these exceptions are generated and typical exception handler operations for handling these exceptions. 15.3.1. Debug Exception (#DB)—Interrupt Vector 1 The debug-exception handler is usually a debugger program or is part of a larger software system. The processor generates a debug exception for any of several conditions. The debu...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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