The processor generates the exception after it

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: gger can check flags in the DR6 and DR7 registers to determine which condition caused the exception and which other conditions might also apply. Table 15-2 shows the states of these flags following the generation of each kind of breakpoint condition. Table 15-2. Debug Exception Conditions Debug or Breakpoint Condition Single-step trap Instruction breakpoint, at addresses defined by DRn and LENn Data write breakpoint, at addresses defined by DRn and LENn I/O read or write breakpoint, at addresses defined by DRn and LENn Data read or write (but not instruction fetches), at addresses defined by DRn and LENn General detect fault, resulting from an attempt to modify debug registers (usually in conjunction with in-circuit emulation) Task switch DR6 Flags Tested BS = 1 Bn = 1 and (GEn or LEn = 1) Bn = 1 and (GEn or LEn = 1) Bn = 1 and (GEn or LEn = 1) Bn = 1 and (GEn or LEn = 1) BD = 1 R/Wn = 0 R/Wn = 1 R/Wn = 2 R/Wn = 3 DR7 Flags Tested Exception Class Trap Fault Trap Trap Trap Fault BT = 1 Trap Instruction-breakpoint and general-detect conditions (refer to Section, “GeneralDetect Exception Condition”) result in faults; other debug-exception conditions result in traps. The debug exception may report either or both at one time. The following sections describe each class of debug exception. Refer to Section 5.12., “Exception and Interrupt Reference” in Chapter 5, Interrupt and Exception Handling for additional information about this exception. INSTRUCTION-BREAKPOINT EXCEPTION CONDITION The processor reports an instruction breakpoint when it attempts to execute an instruction at an address specified in a breakpoint-address register (DB0 through DR3) that has been set up to detect instruction execution (R/W flag is set to 0). Upon reporting the instruction breakpoint, the processor generates a fault-class, debug exception (#DB) before it executes the target instruction 15-8 DEBUGGING AND PERFORMANCE MONITORING for the breakpoint. Instruction breakpoints are the highest priority debug exceptions and are guaranteed to be serviced before any other exceptions that may be detected during the decoding or execution of an instruction. Because the debug exception for an instruction breakpoint is generated before the instruction is executed, if the instruction breakpoint is not removed by the exception handler, the processor will detect the instruction breakpoint again when the instruction is restarted and generate another debug exception. To prevent looping on an instruction breakpoint, the Intel Architecture provides the RF flag (resume flag) in the EFLAGS register (refer to Section 2.3., “System Flags and Fields in the EFLAGS Register” in Chapter 2, System Architecture Overview). When the RF flag is set, the processor ignores instruction breakpoints. All Intel Architecture processors manage the RF flag as follows. The processor sets the RF flag automatically prior to calling an exception handler for any fault-class exception except a debug exception that was generated in response to an instruction breakpoint. For debug exceptions resulting from instruction breakpoints, the processor does not set the RF flag prior to calling the debug exception handler. The debug exception handler then has the option of disabling the instruction breakpoint or setting the RF flag in the EFLAGS image on the stack. If the RF flag in the EFLAGS image is set when the processor returns from the exception handler, it is copied into the RF flag in the EFLAGS register by the IRETD or task switch instruction that causes the return. The processor then ignores instruction breakpoints for the duration of the next instruction. (Note that the POPF, POPFD, and IRET instructions do not transfer the RF image into the EFLAGS register.) Setting the RF flag does not prevent other types of debug-exception conditions (such as, I/O or data breakpoints) from being detected, nor does it prevent nondebug exceptions from being generated. After the instruction is successfully executed, the processor clears the RF flag in the EFLAGS register, except after an IRETD instruction or after a JMP, CALL, or INT n instruction that causes a task switch. (Note that the processor also does not set the RF flag when calling exception or interrupt handlers for trap-class exceptions, for hardware interrupts, or for software-generated interrupts.) For the Pentium® processor, when an instruction breakpoint coincides with another fault-type exception (such as a page fault), the processor may generate one spurious debug exception after the second exception has been handled, even though the debug exception handler set the RF flag in the EFLAGS image. To prevent this spurious exception with Pentium® processors, all faultclass exception handlers should set the RF flag in the EFLAGS image. DATA MEMORY AND I/O BREAKPOINT EXCEPTION CONDITIONS Data memory and I/O breakpoints are reported when the processor attempts to access a memory or I/O address specified in a breakpoint-address register (DB0 through DR3) that has been set up to detect data or I/O accesses (R/W f...
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

Ask a homework question - tutors are online