IntelSoftwareDevelopersManual

The virtual8086 monitor also may need data segment

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ULATION backward compatibility to Intel 8086 processors, the default base address and limit of the interrupt vector table should not be changed.) Up to Entry 255 Entry 3 12 Entry 2 8 Entry 1 4 Segment Selector Interrupt Vector 0* Offset 15 * Interrupt vector number 0 selects entry 0 (called “interrupt vector 0”) in the interrupt vector table. Interrupt vector 0 in turn points to the start of the interrupt handler for interrupt 0. 0 IDTR 0 2 Figure 16-2. Interrupt Vector Table in Real-Address Mode Table 16-1 shows the interrupt and exception vectors that can be generated in real-address mode and virtual-8086 mode, and in the Intel 8086 processor. Refer to Chapter 5, Interrupt and Exception Handling for a description of the exception conditions. 16-7 8086 EMULATION Table 16-1. Real-Address Mode Exceptions and Interrupts Vector No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20-31 32-255 NOTE: * In the real-address mode, vector 13 is the segment overrun exception. In protected and virtual-8086 modes, this exception covers all general-protection error conditions, including traps to the virtual-8086 monitor from virtual-8086 mode. Description Divide Error (#DE) Debug Exception (#DB) NMI Interrupt Breakpoint (#BP) Overflow (#OF) BOUND Range Exceeded (#BR) Invalid Opcode (#UD) Device Not Available (#NM) Double Fault (#DF) (Intel reserved. Do not use.) Invalid TSS (#TS) Segment Not Present (#NP) Stack Fault (#SS) General Protection (#GP)* Page Fault (#PF) (Intel reserved. Do not use.) Floating-Point Error (#MF) Alignment Check (#AC) Machine Check (#MC) SIMD Floating-Point Numeric Error (#XF) (Intel reserved. Do not use.) User Defined Interrupts Real-Address Mode Yes Yes Yes Yes Yes Yes Yes Yes Yes Reserved Reserved Reserved Yes Yes Reserved Reserved Yes Reserved Yes Yes Reserved Yes Virtual-8086 Mode Yes Yes Yes Yes Yes Yes Yes Yes Yes Reserved Yes Yes Yes Yes Yes Reserved Yes Yes Yes Yes Reserved Yes Intel 8086 Processor Yes No Yes Yes Yes Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Yes 16-8 8086 EMULATION 16.2. VIRTUAL-8086 MODE Virtual-8086 mode is actually a special type of a task that runs in protected mode. When the operating-system or executive switches to a virtual-8086-mode task, the processor emulates an Intel 8086 processor. The execution environment of the processor while in the 8086-emulation state is the same as is described in Section 16.1., “Real-Address Mode” for real-address mode, including the extensions. The major difference between the two modes is that in virtual-8086 mode the 8086 emulator uses some protected-mode services (such as the protected-mode interrupt and exception-handling and paging facilities). As in real-address mode, any new or legacy program that has been assembled and/or compiled to run on an Intel 8086 processor will run in a virtual-8086-mode task. And several 8086 programs can be run as virtual-8086-mode tasks concurrently with normal protected-mode tasks, using the processor’s multitasking facilities. 16.2.1. Enabling Virtual-8086 Mode The processor runs in virtual-8086 mode when the VM (virtual machine) flag in the EFLAGS register is set. This flag can only be set when the processor switches to a new protected-mode task or resumes virtual-8086 mode via an IRET instruction. System software cannot change the state of the VM flag directly in the EFLAGS register (for example, by using the POPFD instruction). Instead it changes the flag in the image of the EFLAGS register stored in the TSS or on the stack following a call to an interrupt- or exceptionhandler procedure. For example, software sets the VM flag in the EFLAGS image in the TSS when first creating a virtual-8086 task. The processor tests the VM flag under three general conditions: • • • When loading segment registers, to determine whether to use 8086-style address translation. When decoding instructions, to determine which instructions are not supported in virtual8086 mode and which instructions are sensitive to IOPL. When checking privileged instructions, on page accesses, or when performing other permission checks. (Virtual-8086 mode always executes at CPL 3.) 16.2.2. Structure of a Virtual-8086 Task A virtual-8086-mode task consists of the following items: • • • • A 32-bit TSS for the task. The 8086 program. A virtual-8086 monitor. 8086 operating-system services. 16-9 8086 EMULATION The TSS of the new task must be a 32-bit TSS, not a 16-bit TSS, because the 16-bit TSS does not load the most-significant word of the EFLAGS register, which contains the VM flag. All TSS’s, stacks, data, and code used to handle exceptions when in virtual-8086 mode must also be 32-bit segments. The processor enters virtual-8086 mode to run the 8086 program and returns to protected mode to run the virtual-8086 monitor. The virtual-8086 monitor is a 32-bit protected-mode code module that runs at a CPL of 0. The monitor consists of ini...
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

Ask a homework question - tutors are online