This preview shows page 1. Sign up to view the full content.
Unformatted text preview: le 7-7 describes the interrupt-style abbreviations that will be used through out the remaining description of the MP initialization protocol. These IPIs do not define new interrupt messages. They are messages that are special only by virtue of the time that they exist (that is, before the RESET sequence is complete).
Table 7-7. Types of Boot Phase IPIs
Message Type Boot InterProcessor Interrupt Final Boot InterProcessor Interrupt Abbreviation BIPI FIPI Description An APIC serial bus message that Symmetric Multiprocessing (SMP) agents use to dynamically determine a BSP after reset. An APIC serial bus message that the BSP issues before it fetches from the reset vector. This message has the lowest priority of all boot phase IPIs. When a BSP sees an FIPI that it issued, it fetches the reset vector because no other boot phase IPIs can follow an FIPI. Used to send a new reset vector to a Application Processor (nonBSP) processor in an MP system. Startup InterProcessor Interrupt SIPI Table 7-8 describes the various fields of each boot phase IPI.
Table 7-8. Boot Phase IPI Message Format
Type BIPI FIPI SIPI NOTE: * For all P6 family processors. Destination Field Not used Not used Used Destination Shorthand All including self All including self All allowed Trigger Mode Edge Edge Edge Level Deassert Deassert Assert Destination Mode Don’t Care Don’t Care Physical or Logical Delivery Mode Fixed (000) Fixed (000) StartUp (110) Vector (Hex) 40 to 4E* 10 to 1E 00 to FF 7-47 MULTIPLE-PROCESSOR MANAGEMENT For BIPI and FIPI messages, the lower 4 bits of the vector field are equal to the APIC ID of the processor issuing the message. The upper 4 bits of the vector field of a BIPI or FIPI can be thought of as the “generation ID” of the message. All processors that run symmetric to a P6 family processor will have a generation ID of 0100B or 4H. BIPIs in a system based on the P6 family processors will therefore use vector values ranging from 40H to 4EH (4FH can not be used because FH is not a valid APIC ID). 7.7.3. Error Detection During the MP Initialization Protocol Errors may occur on the APIC bus during the MP initialization phase. These errors may be transient or permanent and can be caused by a variety of failure mechanisms (for example, broken traces, soft errors during bus usage, etc.). All serial bus related errors will result in an APIC checksum or acceptance error. The occurrence of an APIC error causes a processor shutdown. 7.7.4. Error Handling During the MP Initialization Protocol The MP initialization protocol makes the following assumptions: • • • If any errors are detected on the APIC bus during execution of the MP initialization protocol, all processors will shutdown. In a system that conforms to Intel Architecture guidelines, a likely error (broken trace, check sum error during transmission) will result in no more than one processor booting. The MP initialization protocol will be executed by processors even if they fail their BIST sequences. 7.7.5. MP Initialization Protocol Algorithm The MP initialization protocol uses the message passing capabilities of the processor’s local APIC to dynamically determine a boot strap processor (BSP). The algorithm used essentially implements a “race for the flag” mechanism using the APIC bus for atomicity. The MP initialization algorithm is based on the fact that one and only one message is allowed to exist on the APIC bus at a given time and that once the message is issued, it will complete (APIC messages are atomic). Another feature of the APIC architecture that is used in the initialization algorithm is the existence of a round-robin priority mechanism between all agents that use the APIC bus. The MP initialization protocol algorithm performs the following operations in a SMP system (refer to Figure 7-19): 1. After completing their internal BISTs, all processors start their MP initialization protocol sequence by issuing BIPIs to “all including self” (at time t=0). The four least significant bits of the vector field of the IPI contain each processor's APIC ID. The APIC hardware 7-48 MULTIPLE-PROCESSOR MANAGEMENT observes the BNR# (block next request) pin to guarantee that the initial BIPI is not issued on the APIC bus until the BIST sequence is completed for all processors in the system. 2. When the first BIPI completes (at time t=1), the APIC hardware (in each processor) propagates an interrupt to the processor core to indicate the arrival of the BIPI. 3. The processor compares the four least significant bits of the BIPI’s vector field to the processor's APIC ID. A match indicates that the processor should be the BSP and continue the initialization sequence. If the APIC ID fails to match the BIPIs vector field, the processor is essentially the “loser” or not the BSP. The processor then becomes an application processor and should enter a “wait for SIPI” loop. 4. The winner (the BSP) issues an FIPI. The FIPI is issued to “all including self” and is guaranteed to be the last IPI on the APIC bus during the initialization sequence. This is due to the fact that the round-robin priority mechanism forces the winning...
View Full Document
This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10