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These gates differ in the way the processor handles

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Unformatted text preview: UPT AND EXCEPTION HANDLING Figure 5-2 shows the formats for the task-gate, interrupt-gate, and trap-gate descriptors. The format of a task gate used in an IDT is the same as that of a task gate used in the GDT or an LDT (refer to Section 6.2.4., “Task-Gate Descriptor” in Chapter 6, Task Management). The task gate contains the segment selector for a TSS for an exception and/or interrupt handler task. Task Gate 31 16 15 14 13 12 P D P L 87 0 0010 1 4 0 31 16 15 TSS Segment Selector 0 Interrupt Gate 31 16 15 14 13 12 87 54 0 D P L Offset 31..16 P 0D1 1 0 000 4 0 31 16 15 Segment Selector Offset 15..0 0 Trap Gate 31 16 15 14 13 12 87 54 0 D P L Offset 31..16 P 0 D1 1 1 000 4 0 31 16 15 Segment Selector Offset 15..0 0 DPL Offset P Selector D Descriptor Privilege Level Offset to procedure entry point Segment Present flag Segment Selector for destination code segment Size of gate: 1 = 32 bits; 0 = 16 bits Reserved Figure 5-2. IDT Gate Descriptors Interrupt and trap gates are very similar to call gates (refer to Section 4.8.3., “Call Gates” in Chapter 4, Protection). They contain a far pointer (segment selector and offset) that the processor uses to transfer execution to a handler procedure in an exception- or interrupt-handler 5-14 INTERRUPT AND EXCEPTION HANDLING code segment. These gates differ in the way the processor handles the IF flag in the EFLAGS register (refer to Section 5.10.1.2., “Flag Usage By Exception- or Interrupt-Handler Procedure”). 5.10. EXCEPTION AND INTERRUPT HANDLING The processor handles calls to exception- and interrupt-handlers similar to the way it handles calls with a CALL instruction to a procedure or a task. When responding to an exception or interrupt, the processor uses the exception or interrupt vector as an index to a descriptor in the IDT. If the index points to an interrupt gate or trap gate, the processor calls the exception or interrupt handler in a manner similar to a CALL to a call gate (refer to Section 4.8.2., “Gate Descriptors” through Section 4.8.6., “Returning from a Called Procedure” in Chapter 4, Protection). If index points to a task gate, the processor executes a task switch to the exception- or interrupt-handler task in a manner similar to a CALL to a task gate (refer to Section 6.3., “Task Switching” in Chapter 6, Task Management). 5.10.1. Exception- or Interrupt-Handler Procedures An interrupt gate or trap gate references an exception- or interrupt-handler procedure that runs in the context of the currently executing task (refer to Figure 5-3). The segment selector for the gate points to a segment descriptor for an executable code segment in either the GDT or the current LDT. The offset field of the gate descriptor points to the beginning of the exception- or interrupt-handling procedure. When the processor performs a call to the exception- or interrupt-handler procedure, it saves the current states of the EFLAGS register, CS register, and EIP register on the stack (refer to Figure 5-4). (The CS and EIP registers provide a return instruction pointer for the handler.) If an exception causes an error code to be saved, it is pushed on the stack after the EIP value. If the handler procedure is going to be executed at the same privilege level as the interrupted procedure, the handler uses the current stack. If the handler procedure is going to be executed at a numerically lower privilege level, a stack switch occurs. When a stack switch occurs, a stack pointer for the stack to be returned to is also saved on the stack. (The SS and ESP registers provide a return stack pointer for the handler.) The segment selector and stack pointer for the stack to be used by the handler is obtained from the TSS for the currently executing task. The processor copies the EFLAGS, SS, ESP, CS, EIP, and error code information from the interrupted procedure’s stack to the handler’s stack. To return from an exception- or interrupt-handler procedure, the handler must use the IRET (or IRETD) instruction. The IRET instruction is similar to the RET instruction except that it restores the saved flags into the EFLAGS register. The IOPL field of the EFLAGS register is restored only if the CPL is 0. The IF flag is changed only if the CPL is less than or equal to the IOPL. Refer to “IRET/IRETD—Interrupt Return” in Chapter 3 of the Intel Architecture Software Developer’s Manual, Volume 2, for the complete operation performed by the IRET instruction. If a stack switch occurred when calling the handler procedure, the IRET instruction switches back to the interrupted procedure’s stack on the return. 5-15 INTERRUPT AND EXCEPTION HANDLING IDT Destination Code Segment Offset Interrupt Vector Interrupt or Trap Gate + Interrupt Procedure Segment Selector GDT or LDT Base Address Segment Descriptor Figure 5-3. Interrupt Procedure Call 5-16 INTERRUPT AND EXCEPTION HANDLING Stack Usage with No Privilege-Level Change Interrupted Procedure’s and Handler’s Stack ESP Before Transfer to Handler EFLAGS CS EIP Error Code ESP After Trans...
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