IntelSoftwareDevelopersManual

They run much faster than 16 bit code segments on p6

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Unformatted text preview: 2-bit modules. Table 17-1. Characteristics of 16-Bit and 32-Bit Program Modules Characteristic Segment Size Operand Sizes Pointer Offset Size (Address Size) Stack Pointer Size Control Transfers Allowed to Code Segments of This Size 16-Bit Program Modules 0 to 64 KBytes 8 bits and 16 bits 16 bits 16 Bits 16 Bits 32-Bit Program Modules 0 to 4 GBytes 8 bits and 32 bits 32 bits 32 Bits 32 Bits The Intel Architecture processors function most efficiently when executing 32-bit program modules. They can, however, also execute 16-bit program modules, in any of the following ways: • • • • • • In real-address mode. In virtual-8086 mode. System management mode (SMM). As a protected-mode task, when the code, data, and stack segments for the task are all configured as a 16-bit segments. By integrating 16-bit and 32-bit segments into a single protected-mode task. By integrating 16-bit operations into 32-bit code segments. Real-address mode, virtual-8086 mode, and SMM are native 16-bit modes. A legacy program assembled and/or compiled to run on an Intel 8086 or Intel 286 processor should run in realaddress mode or virtual-8086 mode without modification. Sixteen-bit program modules can also be written to run in real-address mode for handling system initialization or to run in SMM for handling system management functions. Refer to Chapter 16, 8086 Emulation for detailed information on real-address mode and virtual-8086 mode; refer to Chapter 12, System Management Mode (SMM) for information on SMM. This chapter describes how to integrate 16-bit program modules with 32-bit program modules when operating in protected mode and how to mix 16-bit and 32-bit code within 32-bit code segments. 17-1 MIXING 16-BIT AND 32-BIT CODE 17.1. DEFINING 16-BIT AND 32-BIT PROGRAM MODULES The following Intel Architecture mechanisms are used to distinguish between and support 16bit and 32-bit segments and operations: • • • • • The D (default operand and address size) flag in code-segment descriptors. The B (default stack size) flag in stack-segment descriptors. 16-bit and 32-bit call gates, interrupt gates, and trap gates. Operand-size and address-size instruction prefixes. 16-bit and 32-bit general-purpose registers. The D flag in a code-segment descriptor determines the default operand-size and address-size for the instructions of a code segment. (In real-address mode and virtual-8086 mode, which do not use segment descriptors, the default is 16 bits.) A code segment with its D flag set is a 32-bit segment; a code segment with its D flag clear is a 16-bit segment. The B flag in the stack-segment descriptor specifies the size of stack pointer (the 32-bit ESP register or the 16-bit SP register) used by the processor for implicit stack references. The B flag for all data descriptors also controls upper address range for expand down segments. When transferring program control to another code segment through a call gate, interrupt gate, or trap gate, the operand size used during the transfer is determined by the type of gate used (16bit or 32-bit), (not by the D-flag or prefix of the transfer instruction). The gate type determines how return information is saved on the stack (or stacks). For most efficient and trouble-free operation of the processor, 32-bit programs or tasks should have the D flag in the code-segment descriptor and the B flag in the stack-segment descriptor set, and 16-bit programs or tasks should have these flags clear. Program control transfers from 16-bit segments to 32-bit segments (and vice versa) are handled most efficiently through call, interrupt, or trap gates. Instruction prefixes can be used to override the default operand size and address size of a code segment. These prefixes can be used in real-address mode as well as in protected mode and virtual-8086 mode. An operand-size or address-size prefix only changes the size for the duration of the instruction. 17.2. MIXING 16-BIT AND 32-BIT OPERATIONS WITHIN A CODE SEGMENT The following two instruction prefixes allow mixing of 32-bit and 16-bit operations within one segment: • • The operand-size prefix (66H) The address-size prefix (67H) These prefixes reverse the default size selected by the D flag in the code-segment descriptor. For example, the processor can interpret the (MOV mem, reg) instruction in any of four ways: 17-2 MIXING 16-BIT AND 32-BIT CODE • In a 32-bit code segment: — Moves 32 bits from a 32-bit register to memory using a 32-bit effective address. — If preceded by an operand-size prefix, moves 16 bits from a 16-bit register to memory using a 32-bit effective address. — If preceded by an address-size prefix, moves 32 bits from a 32-bit register to memory using a 16-bit effective address. — If preceded by both an address-size prefix and an operand-size prefix, moves 16 bits from a 16-bit register to memory using a 16-bit effective address. • In a 16-bit code segment: — Moves 16 bits from a 16-bit register to memory using a 16-bit effective address. — If preceded...
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