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This mtrr setup uses the ability to overlap any two

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Unformatted text preview: uld require physical memory to be present throughout the entire 4-GByte physical memory map. If memory is not provided for the complete memory map, the behaviour of the processor is undefined. 9.12.3. Example Base and Mask Calculations The base and mask values entered into the variable-range MTRR pairs are 24-bit values that the processor extends to 36-bits. For example, to enter a base address of 2 MBytes (200000H) to the MTRRphysBase3 register, the 12 least-significant bits are truncated and the value 000200H is entered into the PhysBase field. The same operation must be performed on mask values. For instance, to map the address range from 200000H to 3FFFFFH (2 MBytes to 4 MBytes), a mask value of FFFE00000H is required. Here again, the 12 least-significant bits of this mask value are truncated, so that the value entered in the PhysMask field of the MTRRphysMask3 register is FFFE00H. This mask is chosen so that when any address in the 200000H to 3FFFFFH range is ANDed with the mask value it will return the same value as when the base address is ANDed with the mask value (which is 200000H). To map the address range from 400000H 7FFFFFH (4 MBytes to 8 MBytes), a base value of 000400H is entered in the PhysBase field and a mask value of FFFC00H is entered in the PhysMask field. Here is a real-life example of setting up the MTRRs for an entire system. Assume that the system has the following characteristics: • • 96 MBytes of system memory is mapped as write-back memory (WB) for highest system performance. A custom 4-MByte I/O card is mapped to uncached memory (UC) at a base address of 64 MBytes. This restriction forces the 96 MBytes of system memory to be addressed from 0 to 64 MBytes and from 68 MBytes to 100 MBytes, leaving a 4-MByte hole for the I/O card. An 8-MByte graphics card is mapped to write-combining memory (WC) beginning at address A0000000H. The BIOS area from 15 MBytes to 16 MBytes is mapped to UC memory. • • 9-25 MEMORY CACHE CONTROL The following settings for the MTRRs will yield the proper mapping of the physical address space for this system configuration. The x0_0x notation is used below to add clarity to the large numbers represented. MTRRPhysBase0 = MTRRPhysMask0 = MTRRPhysBase1 = MTRRPhysMask1 = MTRRPhysBase2 = MTRRPhysMask2 = MTRRPhysBase3 = MTRRPhysMask3 = MTRRPhysBase4 = MTRRPhysMask4 = MTRRPhysBase5 = MTRRPhysMask5 = 0000_0000_0000_0006h 0000_000F_FC00_0800h 0000_0000_0400_0006h 0000_000F_FE00_0800h 0000_0000_0600_0006h 0000_000F_FFC0_0800h 0000_0000_0400_0000h 0000_000F_FFC0_0800h 0000_0000_00F0_0000h 0000_000F_FFF0_0800h 0000_0000_A000_0001h 0000_000F_FF80_0800h Caches 0-64 MB as WB cache type. Caches 64-96 MB as WB cache type. Caches 96-100 MB as WB cache type. Caches 64-68 MB as UC cache type. Caches 15-16 MB as UC cache type Cache A0000000h-A0800000 as WC type. This MTRR setup uses the ability to overlap any two memory ranges (as long as the ranges are mapped to WB and UC memory types) to minimize the number of MTRR registers that are required to configure the memory environment. This setup also fulfills the requirement that two register pairs are left for operating system usage. 9.12.4. Range Size and Alignment Requirement The range that is to be mapped to a variable-range MTRR must meet the following “power of 2” size and alignment rules: 1. The minimum range size is 4 KBytes, and the base address of this range must be on at least a 4-KByte boundary. 2. For ranges greater than 4 KBytes, each range must be of length 2n and its base address must be aligned on a 2n boundary, where n is a value equal to or greater than 12. The baseaddress alignment value cannot be less than its length. For example, an 8-KByte range cannot be aligned on a 4-KByte boundary. It must be aligned on at least an 8-KByte boundary. 9.12.4.1. MTRR PRECEDENCES If the MTRRs are not enabled (by setting the E flag in the MTRRdefType register), then all memory accesses are of the UC memory type. If the MTRRs are enabled, then the memory type used for a memory access is determined as follows: 1. If the physical address falls within the first 1 MByte of physical memory and fixed MTRRs are enabled, the processor uses the memory type stored for the appropriate fixed-range MTRR. 9-26 MEMORY CACHE CONTROL 2. Otherwise, the processor attempts to match the physical address with a memory type range set with a pair of variable-range MTRRs: a. If one variable memory range matches, the processor uses the memory type stored in the MTRRphysBasen register for that range. b. If two or more variable memory ranges match and the memory types are identical, then that memory type is used. c. If two or more variable memory ranges match and one of the memory types is UC, the UC memory type used. d. If two or more variable memory ranges match and the memory types are WT and WB, the WT memory type is used. e. If two or more variable memory ranges match and the memory types are other than UC and WB, the behaviour of the processor is undefined. 3. If no fixed or variable memory range matches, the processor...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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