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This bit is asserted in the mcistatus register if

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Unformatted text preview: code, model-specific error code, and other information error code fields for machine-check errors that occur on the external bus. This information can be used to design a machine-check exception handler for the processor that offers greater granularity for the external bus errors. Table 13-7. Encoding of the MCi_STATUS Register for External Bus Errors Bit No. 0-1 2-3 4-7 Bit Function MCA Error Code MCA Error Code MCA Error Code Undefined. Bit 2 is set to 1 if the access was a special cycle. Bit 3 is set to 1 if the access was a special cycle OR a I/O cycle. 00WR; W = 1 for writes, R = 1 for reads. Bit Description 13-11 MACHINE-CHECK ARCHITECTURE Table 13-7. Encoding of the MCi_STATUS Register for External Bus Errors (Contd.) Bit No. 8-9 10 Bit Function MCA Error Code MCA Error Code Undefined. Set to 0 for all EBL errors. Set to 1 for internal watch-dog timer time-out. For a watch-dog timer time-out, all the MCACOD bits except this bit are set to 0. A watch-dog timer time-out only occurs if the BINIT driver is enabled. Set to 1 for EBL errors. Set to 0 for internal watch-dog timer time-out. Reserved. Reserved. Bit Description 11 12-15 16-18 MCA Error Code MCA Error Code ModelSpecific Error Code ModelSpecific Error Code 19-24 000000 for BQ_DCU_READ_TYPE error. 000010 for BQ_IFU_DEMAND_TYPE error. 000011 for BQ_IFU_DEMAND_NC_TYPE error. 000100 for BQ_DCU_RFO_TYPE error. 000101 for BQ_DCU_RFO_LOCK_TYPE error. 000110 for BQ_DCU_ITOM_TYPE error. 001000 for BQ_DCU_WB_TYPE error. 001010 for BQ_DCU_WCEVICT_TYPE error. 001011 for BQ_DCU_WCLINE_TYPE error. 001100 for BQ_DCU_BTM_TYPE error. 001101 for BQ_DCU_INTACK_TYPE error. 001110 for BQ_DCU_INVALL2_TYPE error. 001111 for BQ_DCU_FLUSHL2_TYPE error. 010000 for BQ_DCU_PART_RD_TYPE error. 010010 for BQ_DCU_PART_WR_TYPE error. 010100 for BQ_DCU_SPEC_CYC_TYPE error. 011000 for BQ_DCU_IO_RD_TYPE error. 011001 for BQ_DCU_IO_WR_TYPE error. 011100 for BQ_DCU_LOCK_RD_TYPE error. 011110 for BQ_DCU_SPLOCK_RD_TYPE error. 011101 for BQ_DCU_LOCK_WR_TYPE error. 000 for BQ_ERR_HARD_TYPE error. 001 for BQ_ERR_DOUBLE_TYPE error. 010 for BQ_ERR_AERR2_TYPE error. 100 for BQ_ERR_SINGLE_TYPE error. 101 for BQ_ERR_AERR1_TYPE error. 1 if FRC error is active. 27-25 ModelSpecific Error Code 28 ModelSpecific Error Code ModelSpecific Error Code 29 1 if BERR is driven. 13-12 MACHINE-CHECK ARCHITECTURE Table 13-7. Encoding of the MCi_STATUS Register for External Bus Errors (Contd.) Bit No. 30 Bit Function ModelSpecific Error Code ModelSpecific Error Code Other Information Other Information BINIT Other Information RESPONSE PARITY ERROR Other Information BUS BINIT Other Information TIMEOUT BINIT Bit Description 1 if BINIT is driven for this processor. 31 Reserved. 32-34 35 Reserved. 1 if BINIT is received from external bus. 36 This bit is asserted in the MCi_STATUS register if this component has received a parity error on the RS[2:0]# pins for a response transaction. The RS signals are checked by the RSP# external pin. 37 This bit is asserted in the MCi_STATUS register if this component has received a hard error response on a split transaction (one access that has needed to be split across the 64-bit external bus interface into two accesses). This bit is asserted in the MCi_STATUS register if this component has experienced a ROB time-out, which indicates that no microinstruction has been retired for a predetermined period of time. A ROB time-out occurs when the 15bit ROB time-out counter carries a 1 out of its high order bit. The timer is cleared when a microinstruction retires, an exception is detected by the core processor, RESET is asserted, or when a ROB BINIT occurs. The ROB time-out counter is prescaled by the 8-bit PIC timer which is a divide by 128 of the bus clock (the bus clock is 1:2, 1:3, 1:4 the core clock). When a carry out of the 8-bit PIC timer occurs, the ROB counter counts up by one. While this bit is asserted, it cannot be overwritten by another error. 38 39-41 42 Other Information Other Information HARD ERROR Other Information IERR Other Information AERR Reserved. This bit is asserted in the MCi_STATUS register if this component has initiated a bus transactions which has received a hard error response. While this bit is asserted, it cannot be overwritten. This bit is asserted in the MCi_STATUS register if this component has experienced a failure that causes the IERR pin to be asserted. While this bit is asserted, it cannot be overwritten. This bit is asserted in the MCi_STATUS register if this component has initiated 2 failing bus transactions which have failed due to Address Parity Errors (AERR asserted). While this bit is asserted, it cannot be overwritten. 43 44 13-13 MACHINE-CHECK ARCHITECTURE Table 13-7. Encoding of the MCi_STATUS Register for External Bus Errors (Contd.) Bit No. 45 Bit Function Other Information UECC Other Information CECC Other Information SYNDROME Bit Description Uncorrectable ECC error bit is asserted in the MCi_STATUS register for uncorrected ECC errors. While this b...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

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