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Unformatted text preview: Management and Initialization. Defines the state of an Intel Architecture processor and its floating-point and SIMD floating-point units after reset initialization. This chapter also explains how to set up an Intel Architecture processor for real-address mode operation and protected- mode operation, and how to switch between modes. Chapter 9 — Memory Cache Control. Describes the general concept of caching and the caching mechanisms supported by the Intel Architecture. This chapter also describes the memory type range registers (MTRRs) and how they can be used to map memory types of physical memory. MTRRs were introduced into the Intel Architecture with the Pentium® Pro processor. It also presents information on using the new cache control and memory streaming instructions introduced with the Pentium® III processor. Chapter 10 — MMX™ Technology System Programming. Describes those aspects of the Intel MMX™ technology that must be handled and considered at the system programming level, including task switching, exception handling, and compatibility with existing system environments. The MMX™ technology was introduced into the Intel Architecture with the Pentium® processor. Chapter 11 — Streaming SIMD Extensions System Programming. Describes those aspects of Streaming SIMD Extensions that must be handled and considered at the system programming level, including task switching, exception handling, and compatibility with existing system environments. Streaming SIMD Extensions were introduced into the Intel Architecture with the Pentium® processor. Chapter 12 — System Management Mode (SMM). Describes the Intel Architecture’s system management mode (SMM), which can be used to implement power management functions. 1-2 ABOUT THIS MANUAL Chapter 13 — Machine-Check Architecture. Describes the machine-check architecture, which was introduced into the Intel Architecture with the Pentium® processor. Chapter 14 — Code Optimization. Discusses general optimization techniques for programming an Intel Architecture processor. Chapter 15 — Debugging and Performance Monitoring. Describes the debugging registers and other debug mechanism provided in the Intel Architecture. This chapter also describes the time-stamp counter and the performance-monitoring counters. Chapter 16 — 8086 Emulation. Describes the real-address and virtual-8086 modes of the Intel Architecture. Chapter 17 — Mixing 16-Bit and 32-Bit Code. Describes how to mix 16-bit and 32-bit code modules within the same program or task. Chapter 18 — Intel Architecture Compatibility. Describes the programming differences between the Intel 286, Intel386™, Intel486™, Pentium®, and P6 family processors. The differences among the 32-bit Intel Architecture processors (the Intel386™, Intel486™, Pentium®, and P6 family processors) are described throughout the three volumes of the Intel Architecture Software Developer’s Manual, as relevant to particular features of the architecture. This chapter provides a collection of all the relevant compatibility information for all Intel Architecture processors and also describes the basic differences with respect to the 16-bit Intel Architecture processors (the Intel 8086 and Intel 286 processors). Appendix A — Performance-Monitoring Events. Lists the events that can be counted with the performance-monitoring counters and the codes used to select these events. Both Pentium® processor and P6 family processor events are described. Appendix B — Model-Specific Registers (MSRs). Lists the MSRs available in the Pentium® and P6 family processors and their functions. Appendix C — Dual-Processor (DP) Bootup Sequence Example (Specific to Pentium® Processors). Gives an example of how to use the DP protocol to boot two Pentium® processors (a primary processor and a secondary processor) in a DP system and initialize their APICs. Appendix D — Multiple-Processor (MP) Bootup Sequence Example (Specific to P6 Family Processors). Gives an example of how to use of the MP protocol to boot two P6 family processors in a MP system and initialize their APICs. Appendix E — Programming the LINT0 and LINT1 Inputs. Gives an example of how to program the LINT0 and LINT1 pins for specific interrupt vectors. 1.3. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 1: BASIC ARCHITECTURE The contents of the Intel Architecture Software Developer’s Manual, Volume 1 are as follows: Chapter 1 — About This Manual. Gives an overview of all three volumes of the Intel Architecture Software Developer’s Manual. It also describes the notational conventions in these 1-3 ABOUT THIS MANUAL manuals and lists related Intel manuals and documentation of interest to programmers and hardware designers. Chapter 2 — Introduction to the Intel Architecture. Introduces the Intel Architecture and the families of Intel processors that are based on this architecture. It also gives an overview of the common features found in these processors and brief history of the Intel Architecture. Chapter 3 — Basic Execution Environment. Introduces the m...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10