IntelSoftwareDevelopersManual

This code is not required if an intel 487 sx math

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Unformatted text preview: precedes a floating-point instruction (one which itself automatically synchronizes with the previous floating-point instruction), the WAIT/FWAIT instruction is treated as a no-op. Pending floating-point exceptions from a previous floating-point instruction are processed not on the WAIT/FWAIT instruction but on the floating-point instruction following the WAIT/FWAIT instruction. In such a case, the report of a floating-point exception may appear one instruction later on the Intel486™ processor than on a P6 family or Pentium® FPU, or on Intel 387 math coprocessor. 18.12.11.Operands Split Across Segments and/or Pages On the P6 family, Pentium®, and Intel486™ processor FPUs, when the first half of an operand to be written is inside a page or segment and the second half is outside, a memory fault can cause the first half to be stored but not the second half. In this situation, the Intel 387 math coprocessor stores nothing. 18-18 INTEL ARCHITECTURE COMPATIBILITY 18.12.12.FPU Instruction Synchronization On the 32-bit Intel Architecture FPUs, all floating-point instructions are automatically synchronized; that is, the processor automatically waits until the previous floating-point instruction has completed before completing the next floating-point instruction. No explicit WAIT/FWAIT instructions are required to assure this synchronization. For the 8087 math coprocessors, explicit waits are required before each floating-point instruction to ensure synchronization. Although 8087 programs having explicit WAIT instructions execute perfectly on the 32-bit Intel Architecture processors without reassembly, these WAIT instructions are unnecessary. 18.13. SERIALIZING INSTRUCTIONS Certain instructions have been defined to serialize instruction execution to ensure that modifications to flags, registers and memory are completed before the next instruction is executed (or in P6 family processor terminology “committed to machine state”). Because the P6 family processors use branch-prediction and out-of-order execution techniques to improve performance, instruction execution is not generally serialized until the results of an executed instruction are committed to machine state (refer to Chapter 2, Introduction to the Intel Architecture, in the Intel Architecture Software Developer’s Manual, Volume 1). As a result, at places in a program or task where it is critical to have execution completed for all previous instructions before executing the next instruction (for example, at a branch, at the end of a procedure, or in multiprocessor dependent code), it is useful to add a serializing instruction. Refer to Section 7.4., “Serializing Instructions” in Chapter 7, Multiple-Processor Management for more information on serializing instructions. 18.14. FPU AND MATH COPROCESSOR INITIALIZATION Table 8-1 in Chapter 8, Processor Management and Initialization shows the states of the FPUs in the P6 family, Pentium®, Intel486™ processors and of the Intel 387 math coprocessor and Intel 287 coprocessor following a power-up, reset, or INIT, or following the execution of an FINIT/FNINIT instruction. The following is some additional compatibility information concerning the initialization of Intel Architecture FPUs and math coprocessors. 18.14.1. Intel 387 and Intel 287 Math Coprocessor Initialization Following an Intel386™ processor reset, the processor identifies its coprocessor type (Intel 287 or Intel 387 DX math coprocessor) by sampling its ERROR# input some time after the falling edge of RESET# signal and before execution of the first floating-point instruction. The Intel 287 coprocessor keeps its ERROR# output in inactive state after hardware reset; the Intel 387 coprocessor keeps its ERROR# output in active state after hardware reset. Upon hardware reset or execution of the FINIT/FNINIT instruction, the Intel 387 math coprocessor signals an error condition. The P6 family, Pentium®, and Intel486™ processors, like the Intel 287 coprocessor, do not. 18-19 INTEL ARCHITECTURE COMPATIBILITY 18.14.2. Intel486™ SX Processor and Intel 487 SX Math Coprocessor Initialization When initializing an Intel486™ SX processor and an Intel 487 SX math coprocessor, the initialization routine should check the presence of the math coprocessor and should set the FPU related flags (EM, MP, and NE) in control register CR0 accordingly (refer to Section 2.5., “Control Registers” in Chapter 2, System Architecture Overview for a complete description of these flags). Table 18-1 gives the recommended settings for these flags when the math coprocessor is present. The FSTCW instruction will give a value of FFFFH for the Intel486™ SX microprocessor and 037FH for the Intel 487 SX math coprocessor. Table 18-1. Recommended Values of the FP Related Bits for Intel486™ SX Microprocessor/Intel 487 SX Math Coprocessor System CR0 Flags EM MP NE Intel486™ SX Processor Only 1 0 1 0 1 0, for MS-DOS* systems 1, for user-defined exception handler Intel 487 SX Math Coprocessor Present The EM and MP flag...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

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