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Unformatted text preview: fies the event selected in the event select field. For example, for some cache events, the mask is used as a MESI-protocol qualifier of cache states (refer to Table A-1 in Appendix A, Performance-Monitoring Events). USR (user mode) flag (bit 16) Specifies that events are counted only when the processor is operating at privilege levels 1, 2 or 3. This flag can be used in conjunction with the OS flag. OS (operating system mode) flag (bit 17) Specifies that events are counted only when the processor is operating at privilege level 0. This flag can be used in conjunction with the USR flag. 15-16 DEBUGGING AND PERFORMANCE MONITORING 31 Counter Mask 24 23 22 21 20 19 18 17 16 15
I NE VN I U NPEOS SR TC 87 Unit Mask Event Select 0 INV—Invert counter mask EN—Enable counters* INT—APIC interrupt enable PC—Pin control E—Edge detect OS—Operating system mode USR—User Mode * Only available in PerfEvtSel0. Reserved Figure 15-3. PerfEvtSel0 and PerfEvtSel1 MSRs E (edge detect) flag (bit 18) Enables (when set) edge detection of events. The processor counts the number of deasserted to asserted transitions of any condition that can be expressed by the other fields. The mechanism is limited in that it does not permit back-toback assertions to be distinguished. This mechanism allows software to measure not only the fraction of time spent in a particular state, but also the average length of time spent in such a state (for example, the time spent waiting for an interrupt to be serviced). PC (pin control) flag (bit 19) When set, the processor toggles the PMi pins and increments the counter when performance-monitoring events occur; when clear, the processor toggles the PMi pins when the counter overflows. The toggling of a pin is defined as assertion of the pin for a single bus clock followed by deassertion INT (APIC interrupt enable) flag (bit 20) When set, the processor generates an exception through its local APIC on counter overflow. EN (Enable Counters) Flag (bit 22) This flag is only present in the PerfEvtSel0 MSR. When set, performance counting is enabled in both performance-monitoring counters; when clear, both counters are disabled. INV (invert) flag (bit 23) Inverts the result of the counter-mask comparison when set, so that both greater than and less than comparisons can be made. Counter mask field (bits 24 through 31) When nonzero, the processor compares this mask to the number of events 15-17 DEBUGGING AND PERFORMANCE MONITORING counted during a single cycle. If the event count is greater than or equal to this mask, the counter is incremented by one. Otherwise the counter is not incremented. This mask can be used to count events only if multiple occurrences happen per clock (for example, two or more instructions retired per clock). If the counter-mask field is 0, then the counter is incremented each cycle by the number of events that occurred that cycle. 18.104.22.168. PERFCTR0 AND PERFCTR1 MSRS The performance-counter MSRs (PerfCtr0 and PerfCtr1) contain the event or duration counts for the selected events being counted. The RDPMC instruction can be used by programs or procedures running at any privilege level and in virtual-8086 mode to read these counters. The PCE flag in control register CR4 (bit 8) allows the use of this instruction to be restricted to only programs and procedures running at privilege level 0. The RDPMC instruction is not serializing or ordered with other instructions. Thus, it does not necessarily wait until all previous instructions have been executed before reading the counter. Similarly, subsequent instructions may begin execution before the RDPMC instruction operation is performed. Only the operating system, executing at privilege level 0, can directly manipulate the performance counters, using the RDMSR and WRMSR instructions. A secure operating system would set the TSD flag during system initialization to disable direct user access to the performancemonitoring counters, but provide a user-accessible programming interface that emulates the RDPMC instruction. The WRMSR instruction cannot arbitrarily write to the performance-monitoring counter MSRs (PerfCtr0 and PerfCtr1). Instead, the lower-order 32 bits of each MSR may be written with any value, and the high-order 8 bits are sign-extended according to the value of bit 31. This operation allows writing both positive and negative values to the performance counters. 22.214.171.124. STARTING AND STOPPING THE PERFORMANCE-MONITORING COUNTERS The performance-monitoring counters are started by writing valid setup information in the PerfEvtSel0 and/or PerfEvtSel1 MSRs and setting the enable counters flag in the PerfEvtSel0 MSR. If the setup is valid, the counters begin counting following the execution of a WRMSR instruction that sets the enable counter flag. The counters can be stopped by clearing the enable counters flag or by clearing all the bits in the PerfEvtSel0 and PerfEvtSel1 MSRs. Counter 1 alone can be stopped by clearing the PerfEvtSel1 MSR. 126.96.36.199. EVENT AND TIME-STAMP MONITORING SOFTWARE To use the performance-monitoring counters and time-stamp counter, the operating system needs to provide an event-monitoring device driver. This driver should include procedures for handling the following operations: • • Feature checking. Initialize and start counters. 15-18 DEBUGGING AND PERFORMANCE MONITORING • •...
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