This ensures an update of all memory locations before

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: iptor used by the 32-bit processors, indicating the segment is no larger than 64 Kbytes. Default bit—In a code-segment descriptor, the D flag is clear, indicating 16-bit addressing and operands are the default. In a stack-segment descriptor, the D flag is clear, indicating use of the SP register (instead of the ESP register) and a 64-Kbyte maximum segment limit. For information on mixing 16- and 32-bit code in applications, refer to Chapter 17, Mixing 16Bit and 32-Bit Code. 18.26. SEGMENT AND ADDRESS WRAPAROUND This section discusses differences in segment and address wraparound between the P6 family, Pentium®, Intel486™, Intel386™, Intel 286, and 8086 processors. 18.26.1. Segment Wraparound On the 8086 processor, an attempt to access a memory operand that crosses offset 65,535 or 0FFFFH or offset 0 (for example, moving a word to offset 65,535 or pushing a word when the stack pointer is set to 1) causes the offset to wrap around modulo 65,536 or 010000H. With the Intel 286 processor, any base and offset combination that addresses beyond 16 MBytes wraps around to the 1 MByte of the address space. The P6 family, Pentium®, Intel486™, and Intel386™ processors in real-address mode generate an exception in these cases: • • A general-protection exception (#GP) if the segment is a data segment (that is, if the CS, DS, ES, FS, or GS register is being used to address the segment). A stack-fault exception (#SS) if the segment is a stack segment (that is, if the SS register is being used). An exception to this behavior occurs when a stack access is data aligned, and the stack pointer is pointing to the last aligned piece of data that size at the top of the stack (ESP is FFFFFFFCH). When this data is popped, no segment limit violation occurs and the stack pointer will wrap around to 0. The address space of the P6 family, Pentium®, and Intel486™ processors may wraparound at 1 MByte in real-address mode. An external A20M# pin forces wraparound if enabled. On Intel 8086 processors, it is possible to specify addresses greater than 1 MByte. For example, with a selector value FFFFH and an offset of FFFFH, the effective address would be 10FFEFH (1 MByte plus 65519 bytes). The 8086 processor, which can form addresses up to 20 bits long, truncates the uppermost bit, which “wraps” this address to FFEFH. However, the P6 family, Pentium®, and Intel486™ processors do not truncate this bit if A20M# is not enabled. If a stack operation wraps around the address limit, shutdown occurs. (The 8086 processor does not have a shutdown mode nor a limit.) 18-35 INTEL ARCHITECTURE COMPATIBILITY 18.27. WRITE BUFFERS AND MEMORY ORDERING The Pentium® Pro and Pentium® II processors provide a write buffer for temporary storage of writes (stores) to memory (refer to Section 9.11., “Write Buffer”, in Chapter 9, Memory Cache Control). The Pentium® III processor has 4 write buffers. Writes stored in the write buffer(s) are always written to memory in program order, with the exception of “fast string” store operations (refer to Section 7.2.3., “Out of Order Stores From String Operations in P6 Family Processors” in Chapter 7, Multiple-Processor Management). The Pentium® processor has two write buffers, one corresponding to each of the pipelines. Writes in these buffers are always written to memory in the order they were generated by the processor core. It should be noted that only memory writes are buffered and I/O writes are not. The P6 family, Pentium®, and Intel486™ processors do not synchronize the completion of memory writes on the bus and instruction execution after a write. An I/O, locked, or serializing instruction needs to be executed to synchronize writes with the next instruction (refer to Section 7.4., “Serializing Instructions” in Chapter 7, Multiple-Processor Management). The P6 family processors use processor ordering to maintain consistency in the order that data is read (loaded) and written (stored) in a program and the order the processor actually carries out the reads and writes. With this type of ordering, reads can be carried out speculatively and in any order, reads can pass buffered writes, and writes to memory are always carried out in program order. (Refer to Section 7.2., “Memory Ordering” in Chapter 7, Multiple-Processor Management for more information about processor ordering.) The Pentium ® III processor introduced a new instruction to serialize writes and make them globally visible. Memory ordering issues can arise between a producer and a consumer of data. The SFENCE instruction provides a performance-efficient way of ensuring ordering between routines that produce weakly-ordered results and routines that consume this data. No re-ordering of reads occurs on the Pentium® processor, except under the condition noted in Section 7.2.1., “Memory Ordering in the Pentium® and Intel486™ Processors” in Chapter 7, Multiple-Processor Management, and in the following paragraph describing the Intel486™ processor. Specifically, the write buffers are flushed before the IN instru...
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

Ask a homework question - tutors are online