This operation flushes the instruction queue and

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Unformatted text preview: code segment. 8. Execute the LIDT instruction to load the IDTR register with the address and limit of the protected-mode IDT. 9. Execute the STI instruction to enable maskable hardware interrupts and perform the necessary hardware operation to enable NMI interrupts. Random failures can occur if other instructions exist between steps 3 and 4 above. Failures will be readily seen in some situations, such as when instructions that reference memory are inserted between steps 3 and 4 while in System Management mode. 8.8.2. Switching Back to Real-Address Mode The processor switches back to real-address mode if software clears the PE bit in the CR0 register with a MOV CR0 instruction. A procedure that re-enters real-address mode should perform the following steps: 1. Disable interrupts. A CLI instruction disables maskable hardware interrupts. NMI interrupts can be disabled with external circuitry. 2. If paging is enabled, perform the following operations: — Transfer program control to linear addresses that are identity mapped to physical addresses (that is, linear addresses equal physical addresses). — Insure that the GDT and IDT are in identity mapped pages. — Clear the PG bit in the CR0 register. — Move 0H into the CR3 register to flush the TLB. 3. Transfer program control to a readable segment that has a limit of 64 KBytes (FFFFH). This operation loads the CS register with the segment limit required in real-address mode. 4. Load segment registers SS, DS, ES, FS, and GS with a selector for a descriptor containing the following values, which are appropriate for real-address mode: — Limit = 64 KBytes (0FFFFH) — Byte granular (G = 0) — Expand up (E = 0) — Writable (W = 1) — Present (P = 1) — Base = any value The segment registers must be loaded with nonnull segment selectors or the segment registers will be unusable in real-address mode. Note that if the segment registers are not 8-15 PROCESSOR MANAGEMENT AND INITIALIZATION reloaded, execution continues using the descriptor attributes loaded during protected mode. 5. Execute an LIDT instruction to point to a real-address mode interrupt table that is within the 1-MByte real-address mode address range. 6. Clear the PE flag in the CR0 register to switch to real-address mode. 7. Execute a far JMP instruction to jump to a real-address mode program. This operation flushes the instruction queue and loads the appropriate base and access rights values in the CS register. 8. Load the SS, DS, ES, FS, and GS registers as needed by the real-address mode code. If any of the registers are not going to be used in real-address mode, write 0s to them. 9. Execute the STI instruction to enable maskable hardware interrupts and perform the necessary hardware operation to enable NMI interrupts. NOTE All the code that is executed in steps 1 through 9 must be in a single page and the linear addresses in that page must be identity mapped to physical addresses. 8.9. INITIALIZATION AND MODE SWITCHING EXAMPLE This section provides an initialization and mode switching example that can be incorporated into an application. This code was originally written to initialize the Intel386™ processor, but it will execute successfully on the Pentium® Pro, Pentium®, and Intel486™ processors. The code in this example is intended to reside in EPROM and to run following a hardware reset of the processor. The function of the code is to do the following: • • • • Establish a basic real-address mode operating environment. Load the necessary protected-mode system data structures into RAM. Load the system registers with the necessary pointers to the data structures and the appropriate flag settings for protected-mode operation. Switch the processor to protected mode. Figure 8-3 shows the physical memory layout for the processor following a hardware reset and the starting point of this example. The EPROM that contains the initialization code resides at the upper end of the processor’s physical memory address range, starting at address FFFFFFFFH and going down from there. The address of the first instruction to be executed is at FFFFFFF0H, the default starting address for the processor following a hardware reset. The main steps carried out in this example are summarized in Table 8-4. The source listing for the example (with the filename STARTUP.ASM) is given in Example 8-1. The line numbers given in Table 8-4 refer to the source listing. 8-16 PROCESSOR MANAGEMENT AND INITIALIZATION The following are some additional notes concerning this example: • When the processor is switched into protected mode, the original code segment baseaddress value of FFFF0000H (located in the hidden part of the CS register) is retained and execution continues from the current offset in the EIP register. The processor will thus continue to execute code in the EPROM until a far jump or call is made to a new code segment, at which time, the base address in the CS register will be changed. Maskable hardware interrupts are disabled after a hardware reset and should remain disabled until the necessary interrupt handlers have been installed. The NMI interru...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

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