IntelSoftwareDevelopersManual

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Unformatted text preview: STATUS register is set (refer to Section 13.3.2.2., “MCi_STATUS MSR”). The address returned is either 32-bit offset into a segment, 32-bit linear address, or 36-bit physical address, depending upon the type of error encountered. Bits 36 through 63 of this register are reserved for future address expansion and are always read as zeros. 63 36 35 0 Reserved Address Figure 13-6. Machine-Check Bank Address Register 13-6 MACHINE-CHECK ARCHITECTURE 13.3.2.4. MCi_MISC MSR The MCi_MISC MSR contains additional information describing the machine-check error if the MISCV flag in the MCi_STATUS register is set. This register is not implemented in any of the error-reporting register banks for the P6 family processors. 13.3.3. Mapping of the Pentium® Processor Machine-Check Errors to the P6 Family Machine-Check Architecture The Pentium® processor reports machine-check errors using two registers: P5_MC_TYPE and P5_MC_ADDR. The P6 family processors map these registers into the MCi_STATUS and MCi_ADDR registers of the error-reporting register bank that reports on the type of external bus errors reported in the P5_MC_TYPE and P5_MC_ADDR registers. The information in these registers can then be accessed in either of two ways: • • By reading the MCi_STATUS and MCi_ADDR registers as part of a generalized machinecheck exception handler written for a P6 family processor. By reading the P5_MC_TYPE and P5_MC_ADDR registers with the RDMSR instruction. The second access capability permits a machine-check exception handler written to run on a Pentium® processor to be run on a P6 family processor. There is a limitation in that information returned by the P6 family processor will be encoded differently than it is for the Pentium® processor. To run the Pentium® processor machine-check exception handler on a P6 family processor, it must be rewritten to interpret the P5_MC_TYPE register encodings correctly. 13.4. MACHINE-CHECK AVAILABILITY The machine-check architecture and machine-check exception (#MC) are model-specific features. Software can execute the CPUID instruction to determine whether a processor implements these features. Following the execution of the CPUID instruction, the settings of the MCA flag (bit 14) and MCE flag (bit 7) in the EDX register indicate whether the processor implements the machine-check architecture and machine-check exception, respectively. 13.5. MACHINE-CHECK INITIALIZATION To use the processors machine-check architecture, software must initialize the processor to activate the machine-check exception and the error-reporting mechanism. Example 13-1 gives pseudocode for performing this initialization. This pseudocode checks for the existence of the machine-check architecture and exception on the processor, then enables the machine-check exception and the error-reporting register banks. The pseudocode assumes that the machinecheck exception (#MC) handler has been installed on the system. This initialization procedure is compatible with the Pentium® and P6 family processors. 13-7 MACHINE-CHECK ARCHITECTURE Example 13-1. Machine-Check Initialization Pseudocode EXECUTE the CPUID instruction; READ bits 7 (MCE) and 14 (MCA) of the EDX register; IF CPU supports MCE THEN IF CPU supports MCA THEN IF MCG_CAP.MCG_CTL_P = 1 (* MCG_CTL register is present *) Set MCG_CTL register to all 1s; (* enables all MCA features *) FI; COUNT ← MCG_CAP.Count; (* determine number of error-reporting banks supported *) FOR error-reporting banks (1 through COUNT) DO Set MCi_CTL register to all 1s; (* enables logging of all errors except for the MC0_CTL register *) OD FOR error-reporting banks (0 through COUNT) DO Set MCi_STATUS register to all 0s; (* clears all errors *) OD FI; Set the MCE flag (bit 6) in CR4 register to enable machine-check exceptions; FI; The processor can write valid information (such as an ECC error) into the MC i_STATUS registers while it is being powered up. As part of the initialization of the MCE exception handler, software might examine all the MCi_STATUS registers and log the contents of them, then rewrite them all to zeros. This procedure is not included in the initialization pseudocode in Example 13-1. 13.6. INTERPRETING THE MCA ERROR CODES When the processor detects a machine-check error condition, it writes a 16-bit error code in the MCA Error Code field of one of the MCi_STATUS registers and sets the VAL (valid) flag in that register. The processor may also write a 16-bit Model-specific Error Code in the MCi_STATUS register depending on the implementation of the machine-check architecture of the processor. The MCA error codes are architecturally defined for Intel Architecture processors; however, the specific MCi_STATUS register that a code is written into is model specific. To determine the cause of a machine-check exception, the machine-check exception handler must read the VAL flag for each MCi_STATUS register, and, if the flag is set, then read the MCA error code field of the register. It is the encoding of the MCACOD value that determines the type of error being rep...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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