IntelSoftwareDevelopersManual

This save and restore method is required for

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ns, it should check CPUID.XMM to see if this is a Streaming SIMD Extensions-enabled processor. If CPUID.XMM is set, this verifies that the OS can set CR4.OSXMMEXCPT without faulting. The process by which an application detects the existence of Streaming SIMD Extensions as discussed in Section 9.5.1., “Detecting Support for Streaming SIMD Extensions Using the CPUID Instruction” Chapter 9, Programming with the Streaming SIMD Extensions, in the Intel Architecture Software Developer’s Manual, Volume 1. For additional information and examples, see AP-900, Identifying Support for Streaming SIMD Extensions in the Processor and Operating System. Table 11-5. CPUID Bits for Streaming SIMD Extensions Support CPUID bit (EAX = 1) FXSR (EDX bit24) XMM (EDX bit25) Meaning If set, CPU supports FXSAVE/FXRSTOR. The OS can read this bit to determine if it can use FXSAVE/FXRSTOR in place of FSAVE/FRSTOR for context switches. If set, the Streaming SIMD Extensions set is supported by the processor. Table 11-6. CR4 Bits for Streaming SIMD Extensions Support CR4 bit OSFXSR (bit9) OSXMMEXCPT (bit10) Meaning Defaults to clear. If both the CPU and the OS support FXSAVE/FXRSTOR for use during context switches, then the OS will set this bit. Defaults to clear. The OS will set this bit if it supports unmasked SIMD floatingpoint exceptions. 11.4.2. Device Not Available (DNA) Exceptions Streaming SIMD Extensions will cause a DNA Exception (#NM) if the processor attempts to execute a SIMD floating-point instruction while CR0.TS is set. If CPUID.XMM is clear, execu- 11-6 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING tion of any Streaming SIMD Extensions instruction will cause an invalid opcode fault regardless of the state of CR0.TS. 11.4.3. FXSAVE/FXRSTOR as a Replacement for FSAVE/FRSTOR The FXSAVE and FXRSTOR instructions are designed to be a replacement for FSAVE/FRSTOR, to be used by the OS for context switches. These have been optimized to be faster than FSAVE/FRSTOR, while still saving/restoring the additional SIMD floating-point state. To meet this goal, FXSAVE differs from FSAVE in that it does not cause an FINIT to be performed, nor does FXSAVE initialize the SIMD floating-point registers in any way. While FXSAVE/FXRSTOR does save/restore the x87-FP state, FSAVE/FRSTOR does not affect the SIMD floating-point state. This allows for FXSAVE/FXRSTOR and FSAVE/FRSTOR to be nested. State saved with FXSAVE and restored with FRSTOR (and vice versa) will result in incorrect restoration of state in the processor. FXSAVE will not save the SIMD floating-point state (SIMD floating-point registers and MXCSR register) if the CR4.OSFXSR bit is not set. 11.4.4. Numeric Error flag and IGNNE# Streaming SIMD Extensions ignore CR0.NE (treats it as if it were always set) and the IGNNE# pin and always use the vector 19 software exception for error reporting. 11.5. SAVING AND RESTORING THE STREAMING SIMD EXTENSIONS STATE The recommended method of saving and restoring the Streaming SIMD Extensions state is as follows: • • Execute an FXSAVE instruction to write the entire state of the MMX™/FPU, the SIMD floating-point registers, and the SIMD floating-point MXCSR to memory. Execute an FXRSTOR instruction to read the entire saved state of the MMX™/FPU, the SIMDP floating-point registers and the SIMD floating-point MXCSR from memory into the FPU registers and the aliased MMX™ registers. This save and restore method is required for operating systems (see Section 10.6., “Designing Operating System Task and Context Switching Facilities”). Applications can in some cases save and restore only the SIMD floating-point registers, in the following way: • • Execute eight MOVAPS instructions to write the contents of the SIMD floating-point registers XMM0 through XMM7 to memory. Execute a STMXCSR instruction to save the MXCSR register to memory. Execute eight MOVAPS instructions to read the saved contents of the SIMD floating-point registers from memory into the XMM0 through XMM7 registers. Execute a LDMXCSR 11-7 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING instruction to read the saved contents of the MXCSR register from memory into the MXCSR register. 11.6. DESIGNING OPERATING SYSTEM TASK AND CONTEXT SWITCHING FACILITIES When switching from one task or context to another, it is often necessary to save the SIMD floating-point state (just as it is often necessary to save the state of the FPU). As mentioned in the previous chapter, the MMX™ state is aliased on the FPU state. The SIMD floating-point registers in the Pentium® III processor introduce a new state. When designing new SIMD floating-point state saving facilities for an operating system, several approaches are available: • The operating system can require that applications (which will be run as tasks) take responsibility for saving the SIMD floating-point state prior to a task suspension during a task switch and for restoring the SIMD floating-point state when the task is resumed. The application can use either of the state saving and restoring...
View Full Document

This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

Ask a homework question - tutors are online