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Table 10-2 summarizes the effect of MMX™ and floating-point instructions on the tags in the FPU tag word and the corresponding tags in an image of the tag word stored in memory.
Table 10-2. Effect of the MMX™ and Floating-Point Instructions on the FPU Tag Word
Instruction Type MMX™ Instruction MMX™ Instruction Floating-Point Instruction Instruction All (except EMMS) EMMS All (except FXSAVE/FSAVE, FSTENV, FXRSTOR/FRST OR, FLDENV) FXSAVE/FSAVE, FSTENV FPU Tag Word All tags are set to 00B (valid). All tags are set to 11B (empty). Tag for modified floating-point register is set to 00B or 11B. Image of FPU Tag Word Stored in Memory Not affected. Not affected. Not affected. Floating-Point Instruction Tags and register values are read and interpreted; then all tags are set to 11B. Tags are set according to the actual values in the floatingpoint registers; that is, empty registers are marked 11B and valid registers are marked 00B (nonzero), 01B (zero), or 10B (special). Tags are read and interpreted, but not modified. Floating-Point Instruction FXRSTOR/FRST OR, FLDENV All tags marked 11B in memory are set to 11B; all other tags are set according to the value in the corresponding floatingpoint register: 00B (nonzero), 01B (zero), or 10B (special). 10-3 MMX™ TECHNOLOGY SYSTEM PROGRAMMING The values in the fields of the FPU tag word do not affect the contents of the MMX™ registers or the execution of MMX™ instructions. However, the MMX™ instructions do modify the contents of the FPU tag word, as is described in Section 10.2., “The MMX™ State and MMX™ Register Aliasing”. These modifications may affect the operation of the FPU when executing floating-point instructions, if the FPU state is not initialized or restored prior to beginning floating-point instruction execution. Note that the FXSAVE/FSAVE and FSTENV instructions (which save FPU state information) read the FPU tag register and contents of each of the floating-point registers, determine the actual tag values for each register (empty, nonzero, zero, or special), and store the updated tag word in memory. After executing these instructions, all the tags in the FPU tag word are set to empty (11B). Likewise, the EMMS instruction clears MMX™ state from the MMX™/floatingpoint registers by setting all the tags in the FPU tag word to 11B. 10.3. SAVING AND RESTORING THE MMX™ STATE AND REGISTERS
The recommended method of saving and restoring the MMX™ technology state is as follows: • • Execute an FXSAVE/FSAVE/FNSAVE instruction to write the entire state of the MMX™/FPU, the SIMD floating-point registers and the SIMD floating-point MXCSR to memory. Execute an FXRSTOR/FRSTOR instruction to read the entire saved state of the MMX™/FPU, the SIMD floating-point registers and the SIMD floating-point MXCSR from memory into the FPU registers, the aliased MMX™ registers, the SIMD floatingpoint registers and the SIMD floating-point MXCSR. This save and restore method is required for operating systems (refer to Section 10.4., “Designing Operating System Task and Context Switching Facilities”). Applications can in some cases save and restore only the MMX™ registers, in the following way: • • Execute eight MOVQ instructions to write the contents of the MMX™ registers MM0 through MM7 to memory. An EMMS instruction may then (optionally) be executed to clear the MMX™ state in the FPU. Execute eight MOVQ instructions to read the saved contents of the MMX™ registers from memory into the MM0 through MM7 registers.
NOTE Intel does not support scanning the FPU tag word and then only saving valid entries. 10-4 MMX™ TECHNOLOGY SYSTEM PROGRAMMING 10.4. DESIGNING OPERATING SYSTEM TASK AND CONTEXT SWITCHING FACILITIES
When switching from one task or context to another, it is often necessary to save the MMX™ state (just as it is often necessary to save the state of the FPU). As a general rule, if the existing task switching code for an operating system includes facilities for saving the state of the FPU, these facilities can also be relied upon to save the MMX™ state, without rewriting the task switch code. This reliance is possible because the MMX™ state is aliased to the FPU state (refer to Section 10.2., “The MMX™ State and MMX™ Register Aliasing”). When designing new MMX™ (and/or FPU) state saving facilities for an operating system, several approaches are available: • The operating system can require that applications (which will be run as tasks) take responsibility for saving the state of the MMX™/FPU prior to a task suspension during a task switch and for restoring the MMX™/FPU state when the task is resumed. The application can use either of the state saving and restoring techniques given in Section 10.3., “Saving and Restoring the MMX™ State and Registers”. This approach to saving MMX™/FPU state is appropriate for cooperative multitasking operating systems, where the application has control over (or is able to determine) when a task sw...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.
- Spring '10