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Unformatted text preview: the floating-point operation (EM = 1). Ordinarily, the EM flag is cleared when an FPU or math coprocessor is present and set if they are not present. If the EM flag is set and no FPU, math coprocessor, or floating-point emulator is present, the system will hang when a floatingpoint instruction is executed. The MP flag determines whether WAIT/FWAIT instructions react to the setting of the TS flag. If the MP flag is clear, WAIT/FWAIT instructions ignore the setting of the TS flag; if the MP flag is set, they will generate a device-not-available exception (#NM) if the TS flag is set. Generally, the MP flag should be set for processors with an integrated FPU and clear for processors without an integrated FPU and without a math coprocessor present. However, an operating system can choose to save the floating-point context at every context switch, in which case there would be no need to set the MP bit. Table 2-1 in Chapter 2, System Architecture Overview shows the actions taken for floating-point and WAIT/FWAIT instructions based on the settings of the EM, MP, and TS flags. The NE flag determines whether unmasked floating-point exceptions are handled by generating a floating-point error exception internally (NE is set, native mode) or through an external interrupt (NE is cleared). In systems where an external interrupt controller is used to invoke numeric exception handlers (such as MS-DOS-based systems), the NE bit should be cleared. 8-7 PROCESSOR MANAGEMENT AND INITIALIZATION 8.2.2. Setting the Processor for FPU Software Emulation Setting the EM flag causes the processor to generate a device-not-available exception (#NM) and trap to a software exception handler whenever it encounters a floating-point instruction. (Table 8-2 shows when it is appropriate to use this flag.) Setting this flag has two functions: • • It allows floating-point code to run on an Intel processor that neither has an integrated FPU nor is connected to an external math coprocessor, by using a floating-point emulator. It allows floating-point code to be executed using a special or nonstandard floating-point emulator, selected for a particular application, regardless of whether an FPU or math coprocessor is present. To emulate floating-point instructions, the EM, MP, and NE flag in control register CR0 should be set as shown in Table 8-3.
Table 8-3. Software Emulation Settings of EM, MP, and NE Flags
CR0 Bit EM MP NE Value 1 0 1 Regardless of the value of the EM bit, the Intel486™ SX processor generates a device-not-available exception (#NM) upon encountering any floating-point instruction. 8.3. CACHE ENABLING The Intel Architecture processors (beginning with the Intel486™ processor) contain internal instruction and data caches. These caches are enabled by clearing the CD and NW flags in control register CR0. (They are set during a hardware reset.) Because all internal cache lines are invalid following reset initialization, it is not necessary to invalidate the cache before enabling caching. Any external caches may require initialization and invalidation using a system-specific initialization and invalidation code sequence. Depending on the hardware and operating system or executive requirements, additional configuration of the processor’s caching facilities will probably be required. Beginning with the Intel486™ processor, page-level caching can be controlled with the PCD and PWT flags in page-directory and page-table entries. For P6 family processors, the memory type range registers (MTRRs) control the caching characteristics of the regions of physical memory. (For the Intel486™ and Pentium® processors, external hardware can be used to control the caching characteristics of regions of physical memory.) Refer to Chapter 9, Memory Cache Control, for detailed information on configuration of the caching facilities in the P6 family processors and system memory. 8.4. MODEL-SPECIFIC REGISTERS (MSRS) The P6 family processors and Pentium® processors contain model-specific registers (MSRs). These registers are by definition implementation specific; that is, they are not guaranteed to be
8-8 PROCESSOR MANAGEMENT AND INITIALIZATION supported on future Intel Architecture processors and/or to have the same functions. The MSRs are provided to control a variety of hardware- and software-related features, including: • • • • The performance-monitoring counters (refer to Section 15.6., “Performance-Monitoring Counters”, in Chapter 15, Debugging and Performance Monitoring). (P6 family processors only.) Debug extensions (refer to Section 15.4., “Last Branch, Interrupt, and Exception Recording”, in Chapter 15, Debugging and Performance Monitoring). (P6 family processors only.) The machine-check exception capability and its accompanying machine-check architecture (refer to Chapter 13, Machine-Check Architecture). (P6 family processors only.) The MTRRs (refer to Section 9.12., “Memory Type Range Registers (MTRRs)”, in Chapter 9, Memory Cache Control). The MSRs can be read and written to using...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.
- Spring '10