Updates for different steppings are differentiated by

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Unformatted text preview: processor. This feature provides for operating in a mixed stepping environment on an MP system and enables a user to upgrade to a later version of the processor. In this case, modify the loader to check the CPUID and platform ID bits of the processor that it is running on against the available headers before loading a particular update. The number of updates is only limited by the available space in the BIOS. A loader can load the update and test the processor to determine if the update was loaded correctly. This can be done as described in the Section 8.10.3., “Update Signature and Verification”. A loader can verify the integrity of the update data by performing a checksum on the double words of the update summing to zero, and can reject the update. A loader can provide power-on messages indicating successful loading of an update. • • • 8.10.3. Update Signature and Verification The P6 family processor provides capabilities to verify the authenticity of a particular update and to identify the current update revision. This section describes the model-specific extensions of the processor that support this feature. The update verification method below assumes that the BIOS will only verify an update that is more recent than the revision currently loaded into the processor. The CPUID instruction returns a value in a model specific register in addition to its usual register return values. The semantics of the CPUID instruction cause it to deposit an update ID value in the 64-bit model-specific register (MSR) at address 08Bh. If no update is present in the processor, the value in the MSR remains unmodified. Normally a zero value is preloaded into the MSR by software before executing the CPUID instruction. If the MSR still contains zero after executing CPUID, this indicates that no update is present. The update ID value returned in the EDX register after a RDMSR instruction indicates the revision of the update loaded in the processor. This value, in combination with the normal CPUID 8-37 PROCESSOR MANAGEMENT AND INITIALIZATION value returned in the EAX register, uniquely identifies a particular update. The signature ID can be directly compared with the update revision field in the microcode update header for verification of a correct update load. No consecutive updates released for a given stepping of the P6 family processor may share the same signature. Updates for different steppings are differentiated by the CPUID value. DETERMINING THE SIGNATURE An update that is successfully loaded into the processor provides a signature that matches the update revision of the currently functioning revision. This signature is available any time after the actual update has been loaded, and requesting this signature does not have any negative impact upon any currently loaded update. The procedure for determining this signature is: mov ecx, 08Bh;Model Specific Register to Read in ECX xor eax,eax ;clear EAX xor edx,edx ;clear EDX WRMSR ;Load 0 to MSR at 8Bh mov eax,1 CPUID mov ecx, 08BH;Model Specific Register to Read RDMSR ;Read Model Specific Register If there is an update currently active in the processor, its update revision is returned in the EDX register after the RDMSR instruction has completed. AUTHENTICATING THE UPDATE An update may be authenticated by the BIOS using the signature primitive, described above, with the following algorithm: Z = Update revision from the update header to be authenticated; X = Current Update Signature from MSR 8Bh; If (Z > X) Then Load Update that is to be authenticated; Y = New Signature from MSR 8Bh; If (Z == Y) then Success Else Fail Else Fail The algorithm requires that the BIOS only authenticate updates that contain a numerically larger revision than the currently loaded revision, where Current Signature (X) < New Update Revision (Z). A processor with no update loaded should be considered to have a revision equal to zero. This authentication procedure relies upon the decoding provided by the processor to verify an update from a potentially hostile source. As an example, this mechanism in conjunction with other safeguards provides security for dynamically incorporating field updates into the BIOS. 8-38 PROCESSOR MANAGEMENT AND INITIALIZATION 8.10.4. P6 Family Processor Microcode Update Specifications This section describes the interface that an application can use to dynamically integrate processor-specific updates into the system BIOS. In this discussion, the application is referred to as the calling program or caller. The real mode INT15 call specification described here is an Intel extension to an OEM BIOS. This extension allows an application to read and modify the contents of the microcode update data in NVRAM. The update loader, which is part of the system BIOS, cannot be updated by the interface. All of the functions defined in the specification must be implemented for a system to be considered compliant with the specification. The INT15 functions are accessible only from real mo...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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