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When debug extensions are enabled the de flag is set

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Unformatted text preview: t Check) flag. NW—Not write-through. Enables write-throughs and cache invalidation cycles when clear and disables invalidation cycles and write-throughs that hit in the cache when set. CD—Cache disable. Enables the internal cache when clear and disables the cache when set. The Intel486™ processor introduced two new flags in control register CR3: • PCD—Page-level cache disable. The state of this flag is driven on the PCD# pin during bus cycles that are not paged, such as interrupt acknowledge cycles, when paging is enabled. The PCD# pin is used to control caching in an external cache on a cycle-by-cycle basis. PWT—Page-level write-through. The state of this flag is driven on the PWT# pin during bus cycles that are not paged, such as interrupt acknowledge cycles, when paging is enabled. The PWT# pin is used to control write through in an external cache on a cycle-bycycle basis. • 18-22 INTEL ARCHITECTURE COMPATIBILITY 18.16. MEMORY MANAGEMENT FACILITIES The following sections describe the new memory management facilities available in the various Intel Architecture processors and some compatibility differences. 18.16.1. New Memory Management Control Flags The Pentium® Pro processor introduced three new memory management features: physical memory addressing extension, the global bit in page-table entries, and general support for larger page sizes. These features are only available when operating in protected mode. 18.16.1.1. PHYSICAL MEMORY ADDRESSING EXTENSION The new PAE (physical address extension) flag in control register CR4, bit 5, enables 4 additional address lines on the processor, allowing 36-bit physical addresses. This option can only be used when paging is enabled, using a new page-table mechanism provided to support the larger physical address range (refer to Section 3.8., “Physical Address Extension” in Chapter 3, Protected-Mode Memory Management). 18.16.1.2. GLOBAL PAGES The new PGE (page global enable) flag in control register CR4, bit 7, provides a mechanism for preventing frequently used pages from being flushed from the translation lookaside buffer (TLB). When this flag is set, frequently used pages (such as pages containing kernel procedures or common data tables) can be marked global by setting the global flag in a page-directory or page-table entry. On a task switch or a write to control register CR3 (which normally causes the TLBs to be flushed), the entries in the TLB marked global are not flushed. Marking pages global in this manner prevents unnecessary reloading of the TLB due to TLB misses on frequently used pages. Refer to Section 3.7., “Translation Lookaside Buffers (TLBs)” in Chapter 3, ProtectedMode Memory Management for a detailed description of this mechanism. 18.16.1.3. LARGER PAGE SIZES The P6 family processors support large page sizes. This facility is enabled with the PSE (page size extension) flag in control register CR4, bit 4. When this flag is set, the processor supports either 4-KByte or 4-MByte page sizes when normal paging is used and 4-KByte and 2-MByte page sizes when the physical address extension is used. Refer to Section 3.6.1., “Paging Options” in Chapter 3, Protected-Mode Memory Management for more information about large page sizes. 18.16.2. CD and NW Cache Control Flags The CD and NW flags in control register CR0 were introduced in the Intel486™ processor. In the P6 family and Pentium® processors, these flags are used to implement a writeback strategy for the data cache; in the Intel486™ processor, they implement a write-through strategy. Refer 18-23 INTEL ARCHITECTURE COMPATIBILITY to Table 9-4, in Chapter 9, Memory Cache Control for a comparison of these bits on the P6 family, Pentium®, and Intel486™ processors. For complete information on caching, refer to Chapter 9, Memory Cache Control. 18.16.3. Descriptor Types and Contents Operating-system code that manages space in descriptor tables often contains an invalid value in the access-rights field of descriptor-table entries to identify unused entries. Access rights values of 80H and 00H remain invalid for the P6 family, Pentium®, Intel486™, Intel386™, and Intel 286 processors. Other values that were invalid on the Intel 286 processor may be valid on the 32-bit processors because uses for these bits have been defined. 18.16.4. Changes in Segment Descriptor Loads On the Intel386™ processor, loading a segment descriptor always causes a locked read and write to set the accessed bit of the descriptor. On the P6 family, Pentium®, and Intel486™ processors, the locked read and write occur only if the bit is not already set. 18.17. DEBUG FACILITIES The P6 family and Pentium® processors include extensions to the Intel486™ processor debugging support for breakpoints. To use the new breakpoint features, it is necessary to set the DE flag in control register CR4. 18.17.1. Differences in Debug Register DR6 It is not possible to write a 1 to reserved bit 12 in debug status register...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at University of California, Berkeley.

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