When task state is saved in a 16 bit tss the upper 16

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Unformatted text preview: address space, the data and code in those segments can be shared among the tasks that share the LDT. This method of sharing is more selective than sharing through the GDT, because the sharing can be limited • 6-18 TASK MANAGEMENT to specific tasks. Other tasks in the system may have different LDTs that do not give them access to the shared segments. • Through segment descriptors in distinct LDTs that are mapped to common addresses in the linear address space. If this common area of the linear address space is mapped to the same area of the physical address space for each task, these segment descriptors permit the tasks to share segments. Such segment descriptors are commonly called aliases. This method of sharing is even more selective than those listed above, because, other segment descriptors in the LDTs may point to independent linear addresses which are not shared. 6.6. 16-BIT TASK-STATE SEGMENT (TSS) The 32-bit Intel Architecture processors also recognize a 16-bit TSS format like the one used in Intel 286 processors (refer to Figure 6-9). It is supported for compatibility with software written to run on these earlier Intel Architecture processors. The following additional information is important to know about the 16-bit TSS. • • • Do not use a 16-bit TSS to implement a virtual-8086 task. The valid segment limit for a 16-bit TSS is 2CH. The 16-bit TSS does not contain a field for the base address of the page directory, which is loaded into control register CR3. Therefore, a separate set of page tables for each task is not supported for 16-bit tasks. If a 16-bit task is dispatched, the page-table structure for the previous task is used. The I/O base address is not included in the 16-bit TSS, so none of the functions of the I/O map are supported. When task state is saved in a 16-bit TSS, the upper 16 bits of the EFLAGS register and the EIP register are lost. When the general-purpose registers are loaded or saved from a 16-bit TSS, the upper 16 bits of the registers are modified and not maintained. • • • 6-19 TASK MANAGEMENT 15 Task LDT Selector DS Selector SS Selector CS Selector ES Selector DI SI BP SP BX DX CX AX FLAG Word IP (Entry Point) SS2 SP2 SS1 SP1 SS0 SP0 Previous Task Link 0 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 Figure 6-9. 16-Bit TSS Format 6-20 7 Multiple-Processor Management CHAPTER 7 MULTIPLE-PROCESSOR MANAGEMENT The Intel Architecture provides several mechanisms for managing and improving the performance of multiple processors connected to the same system bus. These mechanisms include: • • • • Bus locking and/or cache coherency management for performing atomic operations on system memory. Serializing instructions. (These instructions apply only to the Pentium® and P6 family processors.) Advance programmable interrupt controller (APIC) located on the processor chip. (The APIC architecture was introduced into the Intel Architecture with the Pentium ® processor.) A secondary (level 2, L2) cache. For the P6 family processors, the L2 cache is included in the processor package and is tightly coupled to the processor. For the Pentium® and Intel486™ processors, pins are provided to support an external L2 cache. These mechanisms are particularly useful in symmetric-multiprocessing systems; however, they can also be used in applications where a Intel Architecture processor and a special-purpose processor (such as a communications, graphics, or video processor) share the system bus. The main goals of these multiprocessing mechanisms are as follows: • To maintain system memory coherency—When two or more processors are attempting simultaneously to access the same address in system memory, some communication mechanism or memory access protocol must be available to promote data coherency and, in some instances, to allow one processor to temporarily lock a memory location. To maintain cache consistency—When one processor accesses data cached in another processor, it must not receive incorrect data. If it modifies data, all other processors that access that data must receive the modified data. To allow predictable ordering of writes to memory—In some circumstances, it is important that memory writes be observed externally in precisely the same order as programmed. To distribute interrupt handling among a group of processors—When several processors are operating in a system in parallel, it is useful to have a centralized mechanism for receiving interrupts and distributing them to available processors for servicing. • • • The Intel Architecture’s caching mechanism and cache consistency are discussed in Chapter 9, Memory Cache Control. Bus and memory locking, serializing instructions, memory ordering, and the processor’s internal APIC are discussed in the following sections. 7-1 MULTIPLE-PROCESSOR MANAGEMENT 7.1. LOCKED ATOMIC OPERATIONS The 32-bit Intel Architecture processors support locked atomic operations on locations in system memory. These operations are typically used to manage shared data structures (such as semaphores, segment descriptors, system segments,...
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This note was uploaded on 06/07/2013 for the course ECE 1234 taught by Professor Kwhon during the Spring '10 term at Berkeley.

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