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Unformatted text preview: e processor detects a condition for an unmasked SIMD floating-point application exception, a software handler is invoked immediately at the end of the excepting instruction. The handler is invoked through the SIMD floating-point exception interrupt (vector 19), irrespective of the state of the CR0.NE flag. If an exception is unmasked, but SIMD floating-point unmasked exceptions are not enabled (CR4.OSXMMEXCPT = 0), an invalid opcode fault is generated. However, the corresponding exception bit will still be set in the MXCSR, as it would be if CR4.OSXMMEXCPT =1, since the invalid opcode handler or the user needs to determine the cause of the exception. A typical action of the exception handler is to store x87-FP and SIMD floating-point state information in memory (with the FXSAVE/FXRSTOR instructions) so that it can evaluate the exception and formulate an appropriate response. Other typical exception handler actions can include: • • • • • • • Examine stored x87-FP and SIMD floating-point state information (control/status) to determine the nature of the error. Taking action to correct the condition that caused the error. Clear the exception bits in the x87-FP status word (FSW) or the SIMD floating-point control register (MXCSR) Return to the interrupted program and resume normal execution. In lieu of writing recovery procedures, the exception handler can do one or more of the following: Increment in software an exception counter for later display or printing. Print or display diagnostic information (such as the SIMD floating-point register state). Halt further program execution. When an unmasked exception occurs, the processor will not alter the contents of the source register operands prior to invoking the unmasked handler. Similarly, the integer EFLAGS will also not be modified if an unmasked exception occurs while executing the COMISS or UCOMISS instructions. Exception flags will be updated according to the following rules: • Updating of exception flags is generated by a logical-OR of exception conditions for all sub-operand computations, where the OR is done independently for each type of 11-15 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING exception; for packed computations this means 4 sub-operands and for scalar computations this means 1 sub-operand (the lowest one). • • In the case of only masked exception conditions, all flags will be updated, In the case of an unmasked pre-computation type of exception condition (e.g., denormal input), all flags relating to all pre-computation conditions (masked or unmasked) will be updated, and no subsequent computation is performed (i.e., no post-computation condition can occur if there is an unmasked pre-computation condition). In the case of an unmasked post-computation exception condition, all flags relating to all post-computation conditions (masked or unmasked) will be updated; all pre-computation conditions, which must be masked-only will also be reported. INTERACTION WITH X87 NUMERIC EXCEPTIONS • 18.104.22.168. The Streaming SIMD Extensions control/status register was separated from its x87-FP counterparts to allow for maximum flexibility. Consequently, the Streaming SIMD Extensions architecture is independent of the x87-FP architecture, but has the following implications for x87-FP applications that call Streaming SIMD Extensions-enabled libraries: • • The x87-FP rounding mode specified in FCW will not apply to calls in a Streaming SIMD Extensions library (unless the rounding control in MXCSR is explicitly set to the same mode). x87-FP exception observability may not apply to a Streaming SIMD Extensions library. • An application that expects to catch x87-FP exceptions that occur in an x87-FP library will not be notified if an exception occurs in a Streaming SIMD Extensions library, unless the exception masks enabled in FCW have also been enabled in MXCSR. An application will not be able to unmask exceptions after returning from a Streaming SIMD Extensions library call to detect if an error occurred. A SIMD floating-point exception flag that is already set when the corresponding exception is unmasked will not generate a fault; only the next occurrence of that exception will generate an unmasked fault. An application which checks FSW to determine if any masked exception flags were set during an x87-FP library call will also need to check MXCSR in order to observe a similar occurrence of a masked exception within a Streaming SIMD Extensions library. • • 11.7.3. SIMD Floating-point Numeric Exception Conditions and Masked/Unmasked Responses The following sections describe the various conditions that cause a SIMD floating-point numeric exception to be generated and the masked response of the processor when these conditions are detected. 11-16 STREAMING SIMD EXTENSIONS SYSTEM PROGRAMMING 22.214.171.124. INVALID OPERATION EXCEPTION(#IA) The invalid operation exception occurs in response to an invalid arithmetic operand, or to an invalid combination...
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- Spring '10