Unformatted text preview: 0 kT N a
=103 nm
2 ln
q
qN a
ni ''
Cd si tox
=0.146 '' Cox ox xd ∆ V (1 ) kT 0.0292 V
q Q' kT V V ∆ V kT W '' qvDS
qvDS
kT
kT
iDsub I n 1 e Cox ∆ V exp GS T n 1 e
L q
q
∆V
L qvDS
kT
=2.58x109 1 e Assume vDS >> kT/q, iDsub 2.58 109 A , nearly independent of vDS C Vinitial ∆ Q iDsub t
2 Then, the time required to drop voltage to 50% is t CVinitial
=1.94 104Vinitial s
2iDsub 3. J&B P7.55 1⁄
, is proportion a3nal to is proportional to , so when capacitance is scaling
∗ with factor of , ∝ 4. J&B P7.83
In order to be twice faster compared with the reference inverter with a load of
capacitance of 2C,
,
. The worst path contains 3 NMOS
_ and 2 PMOS, hence
5. J&B P8.6 _ , Because the bitlines a...
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 Fall '08
 Taicheng
 Gate, Transistor, Volt, triode region, upper transistor, intermediate point

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