16-vm-concepts

Vpo virtual page oset vpn virtual page number tlbi

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Unformatted text preview: Unused 25 Carnegie Mellon Today           Address spaces (1) VM as a tool for caching (2) VM as a tool for memory management (3) VM as a tool for memory protec;on Address transla;on 26 Carnegie Mellon VM as a Tool for Memory Protec;on     Extend PTEs with permission bits Page fault handler checks these before remapping   If violated, send process SIGSEGV (segmenta2on fault) Process i: Process j: SUP VP 0: VP 1: VP 2: No No Yes SUP VP 0: VP 1: VP 2: No Yes No READ WRITE Yes Yes Yes No Yes Yes • • • READ WRITE Yes Yes Yes No Yes Yes Address PP 6 PP 4 PP 2 Physical Address Space PP 2 PP 4 PP 6 Address PP 9 PP 6 PP 11 PP 8 PP 9 PP 11 27 Carnegie Mellon Today           Address spaces (1) VM as a tool for caching (2) VM as a tool for memory management (3) VM as a tool for memory protec;on Address transla;on 28 Carnegie Mellon VM Address Transla;on   Virtual Address Space   V = {0, 1, …, N–1}   Physical Address Space   P = {0, 1, …, M–1}   Address Transla;on   MAP: V → P U {∅}   For virtual address a:     MAP(a) = a’ if data at virtual address a is at physical address a’ in P MAP(a) = ∅ if data at virtual address a is not in physical memory –  Either invalid or stored on disk 29 Carnegie Mellon Summary of Address Transla;on Symbols   Basic Parameters   N = 2n : Number of addresses in virtual address space   M = 2m : Number of addresses in physical address space   P = 2p : Page size (bytes)   Components of the virtual address (VA)           VPO: Virtual page offset VPN: Virtual page number TLBI: TLB index TLBT: TLB tag Components of the physical address (PA)           PPO: Physical page offset (same as VPO) PPN: Physical page number CO: Byte offset within cache line CI: Cache index CT: Cache tag 30 Carnegie Mellon Address Transla;on With a Page Table Virtual address Page table base register (PTBR) Page table address for process n ­1 p p ­1 0 Virtual page offset (VPO) Virtual page number (VPN) Page table Valid Physical page number (PPN) Valid bit = 0: page not in memory (page fault) m ­1 Physical page number (PPN) p p ­1 0 Physical page offset (PPO) Physical address 31 Carnegie Mellon Address Transla;on: Page Hit 2 PTEA CPU Chip CPU 1 VA PTE MMU 3 PA Cache/ Memory 4 Data 5 1) Processor sends virtual address to MMU 2 ­3) MMU fetches PTE from page table in memory 4) MMU sends physical address to cache/memory 5) Cache/memory sends data word to processor 32 Carnegie Mellon Address Transla;on: Page Fault Excep;on 4 2 PTEA CPU...
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