Chap_2Lesson05EmsysNew

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Unformatted text preview: ng and Design", Raj Kamal, Publs.: McGraw-Hill Education 4 8051 system Interrupt Features • 8051 permits when executing low- priority ISR the in-between program flow on interrupt to higher priority ISR • Permits masking all by a primary level bit or individual sources by secondary level bits by setting bits in SFR IE • Assigns default priorities • Permits overriding of default priorities by setting bits in SFR IP 2008 Chapter-2 L5: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 5 Vector Addresses An address from where either an ISR of maximum 8-bytes executes or a Jump to a programmed ISR starting address takes place When EA bit (primary level interrupt bit) is set as well as specific interrupt bit (secondary level interrupt bit) is set 2008 Chapter-2 L5: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 6 External hardware Interrupts INT0 and INT1 progr...
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This note was uploaded on 07/24/2013 for the course ECON 101 taught by Professor Kool during the Winter '12 term at Canadian University of Dubai.

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