2 and p32 used for interrupt p32 and p33 as pins for

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Unformatted text preview: ammable for Two external interrupt pins, INT0 and INT1 at P3.2 and P3.2 used for interrupt P3.2 and P3.3 as pins for INT0 and INTI external interrupt pins when bit 7 IE (interrupt enable SFR) EA (enable all) bit is 1, and bits 0 and 2 are 1 and 1, respectively Programmed by TCON lower 4 bits and the IE register bits IE.2 and IE.0 2008 Chapter-2 L5: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 7 INT1 and INT0 status bits Status bit TCON.3 for status of interrupt at INT1 TCON.3 auto resets to 0 when ISR for servicing INT1 interrupt starts. Status bit TCON.1 for status of interrupt at INT0 and TCON.1 auto resets to 0 when ISR for servicing INT0 starts. 2008 Chapter-2 L5: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill Education 8 INT1 and INT0 Edge or level type control bits TCON.2 for type of interrupt at INT1 and is 1 if it is edge-triggered type else 0. TCON.0 for type of interrupt at INT0 and is 1 if it is edge-triggered type else 0. 2008 Chapter-2 L5: &qu...
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